RF/Analog & Linearity performance analysis of a downscaled JL DG MOSFET on GaAs substrate for Analog/mixed signal SOC applications

With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(\mathrm{g}_{\mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(\mathrm{R}_{\mathrm{o}\mathrm{u}\mathrm{t}})$, cut-off frequency $(\mathrm{f}_{\mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\mathrm{d}})$, maximum frequency $(\mathrm{f}_{\max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.