72nd Device Research Conference最新文献_第2页

Artificial synapses using ferroelectric memristors embedded with CMOS Circuit for image recognition 利用嵌入CMOS电路的铁电忆阻器人工突触进行图像识别

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872414

Y. Nishitani, Y. Kaneko, M. Ueda

{"title":"Artificial synapses using ferroelectric memristors embedded with CMOS Circuit for image recognition","authors":"Y. Nishitani, Y. Kaneko, M. Ueda","doi":"10.1109/DRC.2014.6872414","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872414","url":null,"abstract":"Memristors have attracted attention as devices for brain-inspired computing hardware, such as artificial neural networks [1]. Typical neural networks comprise multiple neurons interconnected via synapses. A synapse modulates the signal transmission strength or “weight” between two neurons. Weight controllability is essential to neural network adaptability. Therefore, it is necessary to establish an artificial synapse that can modulate its own electric conductance, which represents the weights. Some researchers have used two-terminal memristors as synapses [2,3]. However, when using conventional memristors, pulses with complex shapes corresponding to what is learned must be prepared and applied to both terminals simultaneously because of their two-terminal structures [4]. Previously, we showed that a programmable synapse function could be implemented on a three-terminal ferroelectric memristor (3T-FeMEM) fabricated on a single crystal oxide substrate, which enabled simple learning schemes [5]. In this work, synapse chips were fabricated by integrating 3T-FeMEMs on CMOS circuits. We then demonstrated on-chip associative memory function using a neural network circuit with these chips.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130513827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Effect of HfO2 and Al2O3 on monolayer MoS2 electronic structure HfO2和Al2O3对MoS2单层电子结构的影响

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872310

A. Valsaraj, Jiwon Chang, L. F. Register, S. Banerjee

引用次数: 0

Electron transport in large-area epitaxial MoS2 大面积外延MoS2的电子输运

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872311

D. Nath, Lu Ma, Chong Hee Lee, Edwin W. Lee, A. Arehart, Yiying Wu, S. Rajan

引用次数: 2

Characteristics of In0.17Al0.83N/AlN/GaN MOSHEMTs with steeper than 60 mV/decade sub-threshold slopes in the deep sub-threshold region 深度亚阈值区斜率大于60 mV/ 10年的In0.17Al0.83N/AlN/GaN MOSHEMTs的特性

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872283

Zongyang Hu, R. Jana, M. Qi, S. Ganguly, B. Song, E. Kohn, D. Jena, H. Xing

{"title":"Characteristics of In0.17Al0.83N/AlN/GaN MOSHEMTs with steeper than 60 mV/decade sub-threshold slopes in the deep sub-threshold region","authors":"Zongyang Hu, R. Jana, M. Qi, S. Ganguly, B. Song, E. Kohn, D. Jena, H. Xing","doi":"10.1109/DRC.2014.6872283","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872283","url":null,"abstract":"Realization of steep sub-threshold slope (SS) transistors requires exploiting carrier transport mechanisms such as tunneling [1], and also alternative gate barrier materials (i.e. ferroelectric materials) with internal voltage gain [2]. Theoretical studies on piezoelectric barriers indicate that it is possible to achieve internal voltage amplification and steep SS in GaN MOSHEMTs by utilizing electrostriction in conjunction with piezoelectricity in AlN and InAlN [3] [4]. Less than 60 mV/decade SS was experimentally observed in GaN MOSHEMTs with InAlN barriers, in which the steep transition was tentatively correlated with the inhomogeneous distribution of polarization in the barrier [5]. However, steep SS were only observed at drain current (Id) near nA/mm regimes, which leads to difficulties in interpretation of experiment data. Understanding of the mechanism of the steep SS in these devices is still unclear and needs more characterization and modeling. In this work we demonstrate InAlN/AlN/GaN MOSHEMTs with less than 60 mV/decade SS in deep sub-threshold regions (1E-8 A/mm and below) at room temperature (RT). Drain voltage and temperature dependent characteristics are provided with analysis for advancing our understanding of this phenomenon.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

InGaAs Double-gate fin-sidewall MOSFET 双栅翅片-侧壁MOSFET

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872376

A. Vardi, Xin Zhao, J. D. del Alamo

引用次数: 6

Feasibility analysis of high-density STTRAM designs with crossbar or shared transistor structures 采用交叉或共用晶体管结构的高密度stram设计的可行性分析

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872413

An Chen

引用次数: 3

Phase change router for nonvolatile logic 用于非易失性逻辑的相变路由器

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872339

Nadim H. Kan'an, H. Silva, A. Gokirmak

引用次数: 4

Measurement and analysis of gate-induced drain leakage in short-channel strained silicon germanium-on-insulator pMOS FinFETs 短通道应变绝缘子上硅锗pMOS finfet栅极感应漏极测量与分析

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872383

K. Balakrishnan, P. Hashemi, J. Ott, E. Leobandung, Dae-gyu Park

{"title":"Measurement and analysis of gate-induced drain leakage in short-channel strained silicon germanium-on-insulator pMOS FinFETs","authors":"K. Balakrishnan, P. Hashemi, J. Ott, E. Leobandung, Dae-gyu Park","doi":"10.1109/DRC.2014.6872383","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872383","url":null,"abstract":"Strained silicon germanium (s-SiGe) pMOS finFETs have proven benefits over silicon p-MOSFETs due to their superior transport properties which is attributed to uniaxial stress-induced lower hole effective mass [1-2]. However, the narrower bandgap of SiGe compared to silicon leads to an increase in band-to-band tunneling, which results in higher gate-induced drain leakage (GIDL). Previous work has focused on understanding long-channel GIDL for planar buried-channel s-SiGe pFETs with Si cap and ion-implanted source/drain [3,4]. In this work, for the first time, we investigate the short channel GIDL characteristics of surface-channel strained-Si1-xGex (x=0.27 and 0.5) p-MOSFETs in a finFET architecture using a Si-cap-free surface passivation and ion implant-free raised S/D process. We show devices having a minimum GIDL current of 1nA/um for x=0.27 and 20nA/um for x=0.5 at an operating voltage of VDD=0.8V and an operating temperature of 50°C. In addition, temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling (BTBT) is the dominant leakage mechanism as compared to trap-assisted tunneling (TAT) for both cases.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Thin-film circuits for scalable interfacing between large-area electronics and CMOS ICs 用于大面积电子器件和CMOS集成电路之间可扩展接口的薄膜电路

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872402

T. Moy, W. Rieutort-Louis, Yingzhe Hu, Liechao Huang, J. Sanz-Robinson, J. Sturm, S. Wagner, N. Verma

{"title":"Thin-film circuits for scalable interfacing between large-area electronics and CMOS ICs","authors":"T. Moy, W. Rieutort-Louis, Yingzhe Hu, Liechao Huang, J. Sanz-Robinson, J. Sturm, S. Wagner, N. Verma","doi":"10.1109/DRC.2014.6872402","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872402","url":null,"abstract":"Hybrid systems based on large-area electronics (LAE) and CMOS ICs aim to exploit the complementary strengths of the two technologies: the scalability of LAE for forming interconnects and transducers (for sensing and energy harvesting), and the energy efficiency of CMOS for instrumentation and computation. The viability of large-scale systems depends on maximizing the robustness and minimizing the number of interfaces between the LAE and CMOS domains. To maximize robustness, inductive and capacitive coupling has been explored, avoiding the need for metallurgical bonding [1]. To minimize the number of interfaces, a method to access and readout individual sensors via minimal coupling channels, is crucial. In this abstract, we present a thin-film transistor (TFT) based scanning circuit that requires only three capacitively-coupled control signals from the IC to sequentially access an arbitrarily large number of LAE sensors, enabling a single readout interface (Fig. 1). A key attribute of the presented circuit is the low power consumption, which remains nearly constant even as the number of sensors scales.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130073379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Nanometer InP electron devices for VLSI and THz applications 用于VLSI和THz应用的纳米InP电子器件

72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872374

M. Rodwell, S. Lee, C. Huang, D. Elias, V. Chobpattanna, J. Rode, H. Chiang, P. Choudhary, R. Maurer, M. Urteaga, B. Brar, A. Gossard, S. Stemmer

引用次数: 11