Phase change router for nonvolatile logic

Abstract

Phase change memory is moving into the main stream and this technology offers the possibility of integration of high-density high-speed non-volatile memory banks atop CMOS in the same package (Figure 1). Elimination of the memory access latencies associated with the I/O bottleneck will allow CPUs to operate more than 1000x faster and at a fraction of the energy. The two main challenges facing this major breakthrough at the present day are (1) the phase-change memory reliability, and (2) the CMOS foot-print associated with the memory cells and the access circuitry. Recent advances in phase-change materials and device research is expected to yield the desired device reliability and cross-bar arrays are expected to reduce the CMOS access circuitry (foot-print on the CMOS layer) sufficiently to integrate 100s of GB memory onto the CPU. Moving some of the logic and the memory controls to the PCM level will significantly relieve the area concerns in the underlying CMOS layer.