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Securing Reusable Hardware IP cores using Palmprint Biometric 使用掌纹生物识别技术保护可重用硬件IP核
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00099
Rahul Chaurasia, A. Sengupta
{"title":"Securing Reusable Hardware IP cores using Palmprint Biometric","authors":"Rahul Chaurasia, A. Sengupta","doi":"10.1109/iSES52644.2021.00099","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00099","url":null,"abstract":"This paper presents a novel contact-less palmprint biometric based approach for securing reusable hardware IP cores against piracy threat. As the modern integrated circuits (ICs) supply chain involves third party vendors to meet the market demand, an unauthorized intellectual property (IP) vendor may counterfeit the hardware IPs and infuse them into the design. Thus, fake IPs or ICs may unknowingly or deliberately be assimilated into consumer electronics (CE) systems, leading to reliability and safety concerns for end consumers. In the proposed approach, the authentic palmprint biometric is first converted into its equivalent palmprint signature digital template based on a selected feature set. Subsequently, embedding of the palmprint signature’s digital template in the form of secret biometric constraints into the design is performed to distinguish between counterfeited and authentic IP core(s). The proposed approach presents a non-replicable and non-vulnerable solution achieving stronger security in terms of temper tolerance (TT) and probability of coincidence (Pc) than the state of the art techniques.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123183517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA based Implementation of Binarized Neural Network for Sign Language Application 基于FPGA的二值化神经网络手语应用实现
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00077
Mohita Jaiswal, Vaidehi Sharma, Abhishek Sharma, Sandeep Saini, Raghuvir Tomar
{"title":"FPGA based Implementation of Binarized Neural Network for Sign Language Application","authors":"Mohita Jaiswal, Vaidehi Sharma, Abhishek Sharma, Sandeep Saini, Raghuvir Tomar","doi":"10.1109/iSES52644.2021.00077","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00077","url":null,"abstract":"In the last few years, there is an increasing demand for developing efficient solutions for computer vision-related tasks on FPGA hardware due to its quick prototyping and computing capabilities. Therefore, this work aims to implement a low precision Binarized Neural Network (BNN) using a Python framework on the Xilinx PYNQZ2 embedded platform to tackle the challenging problem of Sign Language recognition. More specifically, the FINN framework is adopted and the BNN topology is modified to adapt large resolution (i.e 64x64) to perform classification of proposed Indian Sign Language (ISL) gestures into corresponding numbers. In addition, data augmentation techniques are also applied to improve the overall performance of the neural network. Furthermore, hardware/software co-verification of BNN topology is performed to validate the accuracy after implementing it onto hardware. Extensive experimental results show that it achieves a classification rate of 843.8 frames per second (FPS) on PYNQ-Z2 FPGA which delivers higher performance as compared to previous works. Also, the post-implementation results are analyzed in terms of resource utilization and power consumption.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem 安全物联网生态系统的双向触发三态触发器物理不可克隆功能
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00022
Hemavathy Sriramulu, V. S. K. Bhaaskaran
{"title":"Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem","authors":"Hemavathy Sriramulu, V. S. K. Bhaaskaran","doi":"10.1109/iSES52644.2021.00022","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00022","url":null,"abstract":"The sequential circuit in the clock distribution consumes a substantial amount of power in a digital system. The digital circuitry in the security devices requires low power and energy with increased throughput. In this paper, the security of the IoT devices have been realized using Physical Unclonable Functions (PUF). The proposed Double Edge-Triggered Tristate Flip-Flop PUF (DETTFF PUF) demonstrates significantly enhanced PUF metrics and robustness. The reduced power and energy of the proposed architecture can make DETTFF PUF a preferable choice in the IoT ecosystem. Comparison against the conventional double edge-triggered flip-flops to validate the structure. The design is also compared with conventional double edge-triggered flip-flops to elucidate the significance of the proposed architecture.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Steep Switching NCFET based Logic for Future Energy Efficient Electronics 基于NCFET的陡峭开关逻辑用于未来的节能电子产品
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00083
R. C. Bheemana, A. Japa, S. Yellampalli, R. Vaddi
{"title":"Steep Switching NCFET based Logic for Future Energy Efficient Electronics","authors":"R. C. Bheemana, A. Japa, S. Yellampalli, R. Vaddi","doi":"10.1109/iSES52644.2021.00083","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00083","url":null,"abstract":"Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness $(t_{fe})$ in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits $1.22times$ higher ON current, $66times$ lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates $3.3times$ lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least $3times$ lower energy consumption compared to baseline designs at 0.5V.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and Performance Comparisons of Tri-State Buffer Driver in Graphene, TMDC, and CNT-Based Transistor Technologies 石墨烯、TMDC和碳纳米管晶体管中三态缓冲驱动器的设计和性能比较
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00074
Naheem Olakunle Adesina, Md Azmot Ullah Khan, Jian Xu
{"title":"Design and Performance Comparisons of Tri-State Buffer Driver in Graphene, TMDC, and CNT-Based Transistor Technologies","authors":"Naheem Olakunle Adesina, Md Azmot Ullah Khan, Jian Xu","doi":"10.1109/iSES52644.2021.00074","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00074","url":null,"abstract":"With increasing number of transistors on a chip and improved circuit’s performance, microelectronic devices are continuously scaled down in dimension. Similarly, the end of era of Moore’s law is approaching, so another energy-efficient devices are sought after in order to continue the International Technology Roadmap for Semiconductor (ITRS). Sequel to extending Moore’s law, alternative devices such as graphene-based transistor, transition metal dichalcogenide (TMDC) and carbon nanotube (CNT) transistors are proposed and introduced. In this work, we examine the design of tri-state buffer driver using CMOS transistor, graphene nanoribbon tunnel field effect transistor (GNR TFET), molybdenum disulphide-based dual gate TFET, and carbon nanotube FET, and compare their performance in terms of power consumption, delay, and power delay product (PDP). The simulation results from SPICE and Cadence/Spectre show that CMOS-based tri-state buffer has the worst delay of $sim$ 255 ps at 0.5 V supply voltage. GNR TFET delay has the least delay because of its high on/off ratio. For power consumption, CMOS technology consumes the highest power because of its high leakage current.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Current Drift in Al2O3 Gated Junctionless pH Sensitive Field Effect Transistor
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00039
Jaydeep Singh Parmar, Asif Bhat, Nawaz Shafi, Ankita Porwal, C. Periasamy, Chitrakant Sahu
{"title":"Analysis of Current Drift in Al2O3 Gated Junctionless pH Sensitive Field Effect Transistor","authors":"Jaydeep Singh Parmar, Asif Bhat, Nawaz Shafi, Ankita Porwal, C. Periasamy, Chitrakant Sahu","doi":"10.1109/iSES52644.2021.00039","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00039","url":null,"abstract":"In this paper, the non-ideal effect, i.e., drain current drift phenomena, has been studied for the first time in the fabricated junctionless ion-sensitive field-effect transistor (JLISFET). The transient analysis has been performed for the measurement of the drain current drift for different pH solutions and gate-bias $(V_{lg})$. The investigations show that hydroxyl ions $OH^{-}$ are responsible for the modification of $Al_{2}O_{3}$ sensing film, which is further responsible for the drain current drift in the JL-ISFET device. A maximum drain current drift of 75.2% and 79.3% have been measured for pH = 9 and $(V_{lg}) = -2V$, respectively. The results verify that the hydroxyl ions play an important role in drain current drift. Furthermore, the effect of channel length lch on drain current and pH sensitivity has also been investigated, and it has been observed that the drain current decreases with the increase in channel length and pH sensitivity is in directly proportional relationship with the lch. The maximum pH sensitivity of 58.2 mV/pH was obtained for a channel length of $25 mu m$.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130986504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hand Gesture Classification Using Grayscale Thermal Images and Convolutional Neural Network 基于灰度热图像和卷积神经网络的手势分类
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00035
Rakesh Reddy Yakkati, Sreenivasa Reddy Yeduri, Linga Reddy Cenkeramaddi
{"title":"Hand Gesture Classification Using Grayscale Thermal Images and Convolutional Neural Network","authors":"Rakesh Reddy Yakkati, Sreenivasa Reddy Yeduri, Linga Reddy Cenkeramaddi","doi":"10.1109/iSES52644.2021.00035","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00035","url":null,"abstract":"We propose a convolutional neural network for classifying grayscale images of hand gestures in this paper. We look at ten different hand gestures collected from various people using a thermal camera for classification. The proposed model’s performance in terms of classification accuracy and inference time is then compared to that of other benchmark models. Using extensive results, we show that the proposed model achieves higher classification accuracy while using a smaller model size. In terms of inference time, we show that the proposed model outperforms benchmark models.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132896347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FPGA Based Digital Filters Design to Remove Noise from ECG Signal 基于FPGA的心电信号噪声去除数字滤波器设计
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00061
A. Bakshi, M. Panigrahy, J. K. Das
{"title":"FPGA Based Digital Filters Design to Remove Noise from ECG Signal","authors":"A. Bakshi, M. Panigrahy, J. K. Das","doi":"10.1109/iSES52644.2021.00061","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00061","url":null,"abstract":"An Electrocardiogram (ECG) is a bioelectrical signal that reflects the state of the heart based on the potential changes in the heart. The ECG signal is a widely used method for the early detection and evaluation of cardiovascular disease (CVD). Different types of noise can contaminate the ECG signal while recording, which can lead to a wrong diagnosis. As a result, a clear ECG signal is essential for effective CVD diagnosis. This paper is about designing an efficient ECG denoising technique using a field programmable gate array (FPGA). To denoise the ECG signal, a High Pass Filter, Moving Average Filter, and Savitzky-Golay Filter is used. The designed filters are tested on different ECG signals taken from the MIT-BIH database by mixing different types of noise and the performance is analyzed using several characteristics such as SNR, MSE, and COR of the filter output signal. The system is implemented using Verilog HDL and simulated on the Vivado simulator.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123902599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Ultra-Low Power Reversible MUX and DEMUX using QCA nanotechnology with energy dissipation 采用QCA纳米技术的超低功耗可逆MUX和DEMUX
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00082
Vasudeva Bevara, P. K. Sanki
{"title":"An Ultra-Low Power Reversible MUX and DEMUX using QCA nanotechnology with energy dissipation","authors":"Vasudeva Bevara, P. K. Sanki","doi":"10.1109/iSES52644.2021.00082","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00082","url":null,"abstract":"With the rapid development of Very Large-Scale Integration (VLSI) technology, it is important to achieve a robust design with low power consumption. CMOS design has been affected by several problems over the past few years. Increasing the dissipation of power is a major problem in CMOS devices and circuits. Reversible computing can solve this issue, and reversible logic circuits serve as the foundation of quantum computing. Quantum-dot Cellular Automata (QCA) can be such a nanoscale technology and thus emerges as a promising alternative to the traditional CMOS VLSI. This work focuses on the design of a reversible multiplexer and demultiplexer in the quantum dot cell automata (QCA) framework. Experimentation reveals that the new reversible mux and demux is superior to the traditional reversible modules. The simulation, layout & energy dissipation of the proposed RMD, RM module has been carried out using the QCA Designer-E simulation tool.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115679348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Performance Assessment of Dual Metal Graded Channel Negative Capacitance Junctionless FET for Digital/Analog field 数字/模拟双金属梯度通道负电容无结场效应管的性能评价
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI: 10.1109/iSES52644.2021.00042
S. Chaudhary, B. Dewan, Chitrakant Sahu, M. Yadav
{"title":"Performance Assessment of Dual Metal Graded Channel Negative Capacitance Junctionless FET for Digital/Analog field","authors":"S. Chaudhary, B. Dewan, Chitrakant Sahu, M. Yadav","doi":"10.1109/iSES52644.2021.00042","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00042","url":null,"abstract":"This work focuses on effect of negative capacitance on the Dual Metal Double Gate Graded Channel Junction Less Transistor(DMGC-JLT). The effect of dual metal with graded channel is combined with NCFET to study Ion/Ioff, SS, transconductance, transconductance generation factor and output conductance in comparison to DMGC-JLT. Simulation was carried out using Silvaco ATLAS tool and MATLAB. MATLAB tool is used to solve the 1-D L-K equation. Analyses of the variation in ferroelctric thickness and doping in channel is also performed. The simulation results showed better Ion/Ioff, lower SS, better transconductance and improvement in other factors which is beneficial for both digital and analog applications. Undoped ${HfO}_{2}$ is used as Ferro-electric Material for inducing the negative capacitance effect in baseline device.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114679917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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