{"title":"基于NCFET的陡峭开关逻辑用于未来的节能电子产品","authors":"R. C. Bheemana, A. Japa, S. Yellampalli, R. Vaddi","doi":"10.1109/iSES52644.2021.00083","DOIUrl":null,"url":null,"abstract":"Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness $(t_{fe})$ in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits $1.22\\times$ higher ON current, $66\\times$ lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates $3.3\\times$ lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least $3\\times$ lower energy consumption compared to baseline designs at 0.5V.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Steep Switching NCFET based Logic for Future Energy Efficient Electronics\",\"authors\":\"R. C. Bheemana, A. Japa, S. Yellampalli, R. Vaddi\",\"doi\":\"10.1109/iSES52644.2021.00083\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness $(t_{fe})$ in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits $1.22\\\\times$ higher ON current, $66\\\\times$ lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates $3.3\\\\times$ lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least $3\\\\times$ lower energy consumption compared to baseline designs at 0.5V.\",\"PeriodicalId\":293167,\"journal\":{\"name\":\"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/iSES52644.2021.00083\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iSES52644.2021.00083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Steep Switching NCFET based Logic for Future Energy Efficient Electronics
Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness $(t_{fe})$ in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits $1.22\times$ higher ON current, $66\times$ lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates $3.3\times$ lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least $3\times$ lower energy consumption compared to baseline designs at 0.5V.