Design and Performance Comparisons of Tri-State Buffer Driver in Graphene, TMDC, and CNT-Based Transistor Technologies

With increasing number of transistors on a chip and improved circuit’s performance, microelectronic devices are continuously scaled down in dimension. Similarly, the end of era of Moore’s law is approaching, so another energy-efficient devices are sought after in order to continue the International Technology Roadmap for Semiconductor (ITRS). Sequel to extending Moore’s law, alternative devices such as graphene-based transistor, transition metal dichalcogenide (TMDC) and carbon nanotube (CNT) transistors are proposed and introduced. In this work, we examine the design of tri-state buffer driver using CMOS transistor, graphene nanoribbon tunnel field effect transistor (GNR TFET), molybdenum disulphide-based dual gate TFET, and carbon nanotube FET, and compare their performance in terms of power consumption, delay, and power delay product (PDP). The simulation results from SPICE and Cadence/Spectre show that CMOS-based tri-state buffer has the worst delay of $\sim$ 255 ps at 0.5 V supply voltage. GNR TFET delay has the least delay because of its high on/off ratio. For power consumption, CMOS technology consumes the highest power because of its high leakage current.