基于FPGA的心电信号噪声去除数字滤波器设计

A. Bakshi, M. Panigrahy, J. K. Das
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引用次数: 2

摘要

心电图(ECG)是一种生物电信号,它反映了基于心脏电位变化的心脏状态。心电信号是一种广泛应用于心血管疾病(CVD)早期检测和评估的方法。在记录时,不同类型的噪声会污染心电信号,从而导致错误的诊断。因此,清晰的心电信号对于有效的CVD诊断至关重要。本文设计了一种基于现场可编程门阵列(FPGA)的高效心电信号去噪技术。采用高通滤波器、移动平均滤波器和Savitzky-Golay滤波器对心电信号进行降噪。设计的滤波器通过混合不同类型的噪声对来自MIT-BIH数据库的不同心电信号进行测试,并使用滤波器输出信号的信噪比、MSE和COR等几个特性分析其性能。该系统采用Verilog HDL实现,并在Vivado模拟器上进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA Based Digital Filters Design to Remove Noise from ECG Signal
An Electrocardiogram (ECG) is a bioelectrical signal that reflects the state of the heart based on the potential changes in the heart. The ECG signal is a widely used method for the early detection and evaluation of cardiovascular disease (CVD). Different types of noise can contaminate the ECG signal while recording, which can lead to a wrong diagnosis. As a result, a clear ECG signal is essential for effective CVD diagnosis. This paper is about designing an efficient ECG denoising technique using a field programmable gate array (FPGA). To denoise the ECG signal, a High Pass Filter, Moving Average Filter, and Savitzky-Golay Filter is used. The designed filters are tested on different ECG signals taken from the MIT-BIH database by mixing different types of noise and the performance is analyzed using several characteristics such as SNR, MSE, and COR of the filter output signal. The system is implemented using Verilog HDL and simulated on the Vivado simulator.
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