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2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI 22nm FDSOI源端DAC驱动器的阻抗校准技术、消除过程和温度变化
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884867
Hossein Ghafarian, H. Ordouei, F. Gerfers
{"title":"Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI","authors":"Hossein Ghafarian, H. Ordouei, F. Gerfers","doi":"10.1109/MWSCAS.2019.8884867","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884867","url":null,"abstract":"This paper studies various impedance calibration techniques applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in a 22nm FDSOI process. The body biasing and parallel branching technique, both take advantages of the FDSOI technology by using the large backgate voltage tuning. To verify the proposed technique, an analytical model of the SST driver is developed and the impedance tuning range of each technique is proven to cover over the full ±3σ process and –40 C to 80 C temperature range. It turns out, that the body biasing technique just covers one third of the process and temperature variations, whereas parallel branching calibrates for all corners at cost of increased power consumption. The obtained simulation results of the complete SST driver using the proposed impedance calibration meet the stringent return loss specifications of the automotive 10GBase-T1 Ethernet standard across ±3σ process corner and –40 C to 80 C temperature range.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies 180nm至28nm技术的Femto/Pico-Watt前馈泄漏自抑制逻辑系列
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885086
J. P. Cerqueira, Jieyu Li, Jiangyi Li, Weifeng He, Mingoo Seok
{"title":"A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies","authors":"J. P. Cerqueira, Jieyu Li, Jiangyi Li, Weifeng He, Mingoo Seok","doi":"10.1109/MWSCAS.2019.8885086","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885086","url":null,"abstract":"We present a novel logic family, titled feedforward leakage self-suppression logic (FLSL), for nanowatt and sub-nanowatt always-on circuits. It addresses the prohibitively long delay of existing ultra-low leakage logic families without requiring sleep or mode control signals to exercise the leakage-suppression mode. Implemented in 180-nm CMOS, the proposed logic family achieves femto-watt per-gate leakage and a fan-out-of-4 (FO4) delay of 10.2 µs, a remarkable speed enhancement of 150X over the prior art in the same process in the same leakage level. We also investigate the impact of technology scaling by designing the FLSL logic family additionally in 65-nm and 28-nm processes. In a 28-nm process, the FLSL can achieve about 70 ns FO4 delay and 10 picowatts per-gate leakage. Finally, we prototype a finite impulse response filter core for physical sensing systems in a 180 nm. The filter can achieve the power consumption of 109 picowatts for sparse, i.e., predominantly constant or slowly changing, input signals at 1 kHz clock frequency.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124616189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Spatiotemporal Pattern Detector 一个时空模式检测器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884799
Robert C. Ivans, Kurtis D. Cantley
{"title":"A Spatiotemporal Pattern Detector","authors":"Robert C. Ivans, Kurtis D. Cantley","doi":"10.1109/MWSCAS.2019.8884799","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884799","url":null,"abstract":"A spatiotemporal pattern detector design is presented which can identify three fundamental spatiotemporal patterns consisting of two spikes (from different neurons or from the same neuron). These fundamental cases provide the building blocks for construction of more complicated arbitrary spatiotemporal patterns. The overall design consists of three primary subcircuits, and the operation of each is described. The detection of the three cases of spatiotemporal patterns, and the detection of a more complicated pattern by a network of Spatiotemporal Pattern Detectors, is then demonstrated through simulation using the Cadence Virtuoso platform.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125079577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Chopper Instrumentation Amplifier with Fully Symmetric Negative Capacitance Generation Feedback Loop and Online Digital Calibration for Input Impedance Boosting 一种具有全对称负电容产生反馈回路和输入阻抗升压在线数字校准的斩波仪表放大器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884858
Safaa A. Abdelfattah, A. Shrivastava, M. Onabajo
{"title":"A Chopper Instrumentation Amplifier with Fully Symmetric Negative Capacitance Generation Feedback Loop and Online Digital Calibration for Input Impedance Boosting","authors":"Safaa A. Abdelfattah, A. Shrivastava, M. Onabajo","doi":"10.1109/MWSCAS.2019.8884858","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884858","url":null,"abstract":"A symmetric chopper instrumentation amplifier architecture with two identical 8-bit digitally programmable capacitor banks and online digital calibration block are presented. Designed for long-term brain signal monitoring applications, the feedback capacitor banks generate negative capacitance to cancel the input capacitance from electrode cables to boost the input impedance to above 2 GΩ at 10 Hz. These banks are controlled by an automatic digital background calibration unit that includes an oscillation prevention scheme to ensure stable operation. A chopping technique is introduced to enhance the noise performance of the instrumentation amplifier in combination with the capacitive feedback loop that also contains chopping switches. The instrumentation amplifier and online calibration blocks are designed in 0.13-µm BiCMOS technology with a 1.2V supply, consuming 115.9 µW and 176 nW, respectively. Simulations show that the amplifier has a 26.9 dB gain, 8.06 KHz bandwidth, 0.52 µV input-referred noise integrated from 0.1-100Hz, and −49.9 dB THD with 1mV peak-to-peak input. The core layout area of the calibration block is 2100 µm2.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128570266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An SSHC Circuit Integrated with an Active Rectifier for Piezoelectric Energy Harvesting 集成有源整流器的SSHC压电能量采集电路
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885264
Liao Wu, Chen Guo, Zhongsheng Chen, D. Ha
{"title":"An SSHC Circuit Integrated with an Active Rectifier for Piezoelectric Energy Harvesting","authors":"Liao Wu, Chen Guo, Zhongsheng Chen, D. Ha","doi":"10.1109/MWSCAS.2019.8885264","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885264","url":null,"abstract":"This paper presents a piezoelectric energy harvesting circuit, which integrates a Synchronized Switch Harvesting on Capacitors (SSHC) and an active rectifier. An SSHC circuit does not require an inductor for voltage flipping, and hence is suitable for an on-chip implementation of the circuit. Existing SSHC circuits require dedicated switch drivers, which increases the circuit complexity to result in high power dissipation. The proposed circuit addresses this problem through integration of SSHC and a rectifier. The proposed circuit is designed in 0.35 μm CMOS technology. The simulation results indicate conversion efficiency of 92%, which is far higher than state-of-art SSHC circuits.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130133602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems 无线定位系统实时距离评估算法的实现
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884966
G. Piccinni, G. Avitabile, G. Coviello, C. Talarico
{"title":"Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems","authors":"G. Piccinni, G. Avitabile, G. Coviello, C. Talarico","doi":"10.1109/MWSCAS.2019.8884966","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884966","url":null,"abstract":"Abstract-The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera’s DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128936560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel GF(2n) Modular Squarers 平行GF(2n)模平方
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884794
Trenton J. Grale, E. Swartzlander
{"title":"Parallel GF(2n) Modular Squarers","authors":"Trenton J. Grale, E. Swartzlander","doi":"10.1109/MWSCAS.2019.8884794","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884794","url":null,"abstract":"Operations over polynomial Galois fields GF(2n) are employed in a variety of cryptographic systems, such as elliptic curve cryptography (ECC). These operations include multiplication and reduction with respect to an irreducible polynomial modulus. Fast parallel multipliers can be designed at the cost of higher die area. In addition to modular multiplication, ECC employs modular squaring. Certain properties of GF(2n) polynomials make computation of squares trivial. Modular reduction of these squares can be performed in less time and with less hardware complexity compared to the general multiplication case. In an ECC processor, a dedicated squaring unit can potentially reduce overall latency with minimal hardware cost. A fully parallel polynomial n-bit squarer is presented with O(log2n) latency, which uses lookup tables to store modular reduction terms. It is compared with and evaluated against a polynomial multiplier of similar design.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126964827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Single-Ended-to-Differential Sampling Technique for Sigma Delta ADCs in X-Ray Detectors x射线探测器中Sigma δ adc的单端差分采样技术
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885204
Hussein Ali, P. Caragiulo, C. Tamma, Xiaobin Xu, B. Markovic, F. Abu-Nimeh, D. Doering, A. Dragone, G. Haller
{"title":"Single-Ended-to-Differential Sampling Technique for Sigma Delta ADCs in X-Ray Detectors","authors":"Hussein Ali, P. Caragiulo, C. Tamma, Xiaobin Xu, B. Markovic, F. Abu-Nimeh, D. Doering, A. Dragone, G. Haller","doi":"10.1109/MWSCAS.2019.8885204","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885204","url":null,"abstract":"A sampling technique for X-ray detectors is presented, which performs a two channel single-ended-to-differential sampling, and buffers the sampled signals serially to the incremental Sigma Delta ADC. This sampling technique maximizes the readout speed of the X-ray detectors, while allowing the ADC to sample the input signal multiple times for reduced thermal noise and higher resolution. The sampler is implemented in 0.25 µm CMOS technology, as a part of a mixed signal processing backend for the pixel signal, consists of buffering, ADC conversion and readout circuits. Measured performance shows a high resolution of >77 dB SNR at 3.3 Kfps, which emphasizes the speed advantage and high linearity of the proposed approach.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127963728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lowest VIN Possible for Switched-Inductor Boost Converters 开关电感升压转换器可能的最低VIN
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885248
Tianyu Chang, G. Rincón-Mora
{"title":"Lowest VIN Possible for Switched-Inductor Boost Converters","authors":"Tianyu Chang, G. Rincón-Mora","doi":"10.1109/MWSCAS.2019.8885248","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885248","url":null,"abstract":"The minimum input voltage from which switched-inductor boost converters can draw power is a critical parameter, especially for power supplies that draw power from low-voltage sources like thermoelectric generators. When a battery is absent or fully discharged, the power supply relies on a millivolt input to wake and supply the system. This paper explains and quantifies what determines this minimum threshold both with and without a charged battery present. Analyses show that CMOS converters can wake with 44 mV, but not output power until the input source voltage vS is 268 mV. With a charged battery, they can transfer energy with 4.6 mV, but not output net power until vS is 64 mV.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128996709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy 分路sar ADC中电容尺寸的系统设计以达到最优冗余
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884954
Alok Keshattiwar, B. Sahoo
{"title":"A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy","authors":"Alok Keshattiwar, B. Sahoo","doi":"10.1109/MWSCAS.2019.8884954","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884954","url":null,"abstract":"This paper proposes a systematic way of sizing capacitors in a split-Successive Approximation Register (SAR) analog-to-digital converter (ADC) so as to achieve optimum redundancy that can take care of comparator noise, comparator offset, and digital-to-analog converter (DAC) finite settling. The capacitor sizing technique to optimally distribute redundancy across all bit-cycling phases, has been demonstrated with system-level simulation using MATLAB for split-SAR with one, two, and three bridge-capacitors . The proposed technique of sizing capacitors to achieve optimum redundancy at every bit-cycling step can be easily extended for split-SAR with arbitrary number of bridge-capacitors.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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