Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI

This paper studies various impedance calibration techniques applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in a 22nm FDSOI process. The body biasing and parallel branching technique, both take advantages of the FDSOI technology by using the large backgate voltage tuning. To verify the proposed technique, an analytical model of the SST driver is developed and the impedance tuning range of each technique is proven to cover over the full ±3σ process and –40 C to 80 C temperature range. It turns out, that the body biasing technique just covers one third of the process and temperature variations, whereas parallel branching calibrates for all corners at cost of increased power consumption. The obtained simulation results of the complete SST driver using the proposed impedance calibration meet the stringent return loss specifications of the automotive 10GBase-T1 Ethernet standard across ±3σ process corner and –40 C to 80 C temperature range.