A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy

This paper proposes a systematic way of sizing capacitors in a split-Successive Approximation Register (SAR) analog-to-digital converter (ADC) so as to achieve optimum redundancy that can take care of comparator noise, comparator offset, and digital-to-analog converter (DAC) finite settling. The capacitor sizing technique to optimally distribute redundancy across all bit-cycling phases, has been demonstrated with system-level simulation using MATLAB for split-SAR with one, two, and three bridge-capacitors . The proposed technique of sizing capacitors to achieve optimum redundancy at every bit-cycling step can be easily extended for split-SAR with arbitrary number of bridge-capacitors.