无线定位系统实时距离评估算法的实现

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI:10.1109/MWSCAS.2019.8884966

G. Piccinni, G. Avitabile, G. Coviello, C. Talarico

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引用次数: 0

摘要

摘要:本文介绍了一种结合OFDM符号特性和Zadoff-Chu数列特性的新型TDOA距离评估算法的FPGA实现。距离评估系统已经在严重的多径干扰下进行了验证，并允许实现始终在目标位置1.2cm以内的精度。该算法是使用Altera的DE2-115开发板上的FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E)实现的。该实现需要大约120k位内存和不到40k个逻辑元素(其中大约30k是寄存器)。

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Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems

Abstract-The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera’s DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).

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2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

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