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2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)最新文献

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Passive Modeling of One-Port Networks Through SOS Orthogonal Rational Functions 基于SOS正交有理函数的单端口网络无源建模
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874945
Francisco Coronado, A. Engin
{"title":"Passive Modeling of One-Port Networks Through SOS Orthogonal Rational Functions","authors":"Francisco Coronado, A. Engin","doi":"10.1109/SPI54345.2022.9874945","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874945","url":null,"abstract":"Signal and power integrity design in the time domain requires equivalent circuit models for interconnects and packages, whose descriptions may only be available as tabulated impedance or admittance parameters. Accurate models for these components should maintain their physical properties including causality, stability, and passivity. Our recent work introduced algorithms based on sum-of-squares (SOS) polynomials to address the problem of generating passive scalar models, such as driving point impedances or admittances, based on an existing causal, stable, but non-passive model. We used a scaled Chebyshev basis to avoid the poor conditioning of the monomial basis in SOS constraints. However, the division by the denominator still impacts the numerical accuracy. In this paper, we improve the conditioning of the problem by embedding the denominator polynomial in the basis, resulting in orthogonalized rational functions through Arnoldi iteration.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114256944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Parametric S-Parameters for PCB based Power Delivery Network Design Using Machine Learning 基于机器学习的PCB供电网络参数设计
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874946
Morten Schierholz, I. Erdin, J. Balachandran, Cheng Yang, C. Schuster
{"title":"Parametric S-Parameters for PCB based Power Delivery Network Design Using Machine Learning","authors":"Morten Schierholz, I. Erdin, J. Balachandran, Cheng Yang, C. Schuster","doi":"10.1109/SPI54345.2022.9874946","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874946","url":null,"abstract":"In this contribution, a methodology using ANN techniques is presented for the analysis and design of power delivery network (PDN) in printed circuit board (PCB) design. The trained artificial neural networks (ANNs) are applied to answer relevant PDN design questions such as PCB resonance frequency and target impedance (TI) violations. Based on PCB geometry and material variations a PDN design space is defined. To train the ANNs, inside the design space a sparse sampling with 10000 physics-based (PB) simulations is performed. The S-parameter database is created using physics based via models which are validated by a commercial full-wave finite element method (FEM) solver in the frequency spectrum of 1MHz to 1GHz. The S-parameters are available in the SI/PI-Database. The flexibility of the unterminated S-parameters is demonstrated by a post processing termination using decoupling capacitor (decap) distributions. Limitations of the data generation are discussed with respect to computational resources and disk space.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":" 45","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114051706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhanced Magnetic Field Shielding with Metamaterial Hourglass Lens 增强磁场屏蔽与超材料沙漏透镜
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874943
D. Sengupta, A. Weisshaar
{"title":"Enhanced Magnetic Field Shielding with Metamaterial Hourglass Lens","authors":"D. Sengupta, A. Weisshaar","doi":"10.1109/SPI54345.2022.9874943","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874943","url":null,"abstract":"This paper presents a novel design for a metamaterial (MM) hourglass lens which can achieve a significant improvement in magnetic field shielding when compared to a MM slab of equal dimensions. The shape of the structure and the material properties of near-zero permeability MM(s) are used to attain this enhancement. The improvement in the magnetic shielding is demonstrated by theoretical studies involving magnetic flux models and 3D full-wave electromagnetic simulations. The operating frequency for this study is chosen to be 13.56 MHz in the ISM band, and the relative permeability of the mu-near-zero MM is considered to have a real component of 0.02 and a loss tangent of 0.01. The MM hourglass lens is constructed using a staircase approximation of planar MM slabs. The mutual inductance of a two-coil system with coils of 5 cm radius at different separation distances and with the MM lens or slab is used to compare the shielding efficiency between the MM structures. The proposed lens design constructed using 15 slabs provides about 12% reduction in mutual inductance at a thickness of 30 mm and about 45% reduction at a thickness of 70 mm when compared to the MM slab for a coil separation distance of 25 cm.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130516528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of a 1.35 mm Coaxial Blind Mating Interconnect for ATE mmWave Applications 用于ATE毫米波应用的1.35 mm同轴盲配合互连的开发
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874936
Bill Rosas, Daniel Lam, José Moreira
{"title":"Development of a 1.35 mm Coaxial Blind Mating Interconnect for ATE mmWave Applications","authors":"Bill Rosas, Daniel Lam, José Moreira","doi":"10.1109/SPI54345.2022.9874936","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874936","url":null,"abstract":"With the continuous increase in the usage of mmWave frequencies for consumer applications, the test and measurement industry needs to keep up and provide interconnect technologies for test and measurement at these frequencies. Automated test equipment vendors face the additional challenge of having to use blind mating interconnects on the test fixture, because a threaded interconnect is not acceptable in a high-volume production testing environment. In this paper we present the development and first results of a blind mating interconnect for automated test equipment based on the upcoming 1.35 mm coaxial connector standard. We describe the mechanical design and integration on the automated test system and also the initial performance results. We will show that this new blind mating interconnect can support frequencies up to 90 GHz.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132201293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Feasibility Analysis of Chip-to-Module Channel Operating at 212 Gbps 212gbps芯片到模块信道的可行性分析
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874926
F. de Paulis, Rick Rabinovich, R. Mellitz, M. Resso
{"title":"Feasibility Analysis of Chip-to-Module Channel Operating at 212 Gbps","authors":"F. de Paulis, Rick Rabinovich, R. Mellitz, M. Resso","doi":"10.1109/SPI54345.2022.9874926","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874926","url":null,"abstract":"The ever-growing demand for higher communication data rates calls for better (wider bandwidth) channels, transmitter and receiver noise and equalization. This is exacerbated when the data-rate is expected to double at each iteration of the interface to be standardized, as it is happening for the Ethernet communications. This paper highlights possible strategies for achieving a reliable channel communication at 200 Gbps based on the Chip-to-Module (C2M) interface typically found in data centers. The budgeting among the channel insertion and return losses, number of crosstalk aggressor channels, quality of Tx and Rx ships in terms of noise and advanced equalization schemes will be analyzed. Guidelines for settings the requirements of the channel architecture will be proposed for the channel reliably working at 200 Gbps for the next generation Ethernet communications.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116556243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Vector Fitting of Noisy Frequency Responses via Smoothing Regularization 基于平滑正则化的噪声频率响应矢量拟合
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874941
A. Carlucci, A. Zanco, R. Trinchero, S. Grivet-Talocia
{"title":"Vector Fitting of Noisy Frequency Responses via Smoothing Regularization","authors":"A. Carlucci, A. Zanco, R. Trinchero, S. Grivet-Talocia","doi":"10.1109/SPI54345.2022.9874941","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874941","url":null,"abstract":"We present a simple and effective strategy to compute reduced-order rational macromodels from noisy frequency responses. The reference macromodeling engine is the basic Vector Fitting (VF) scheme, which is well known to be sensitive to noise in the training data. This problem is here avoided by augmenting the VF cost function with a penalization term related to the second derivative of the model, which effectively acts as a regularizer. The results obtained on a set of noisy measurements of a Surface Acoustic Wave (SAW) filter demonstrate the effectiveness of proposed approach in rejecting noise and producing smooth models.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126249633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bathtub Extrapolation of IBIS-AMI Timing Jitter IBIS-AMI时序抖动的浴缸外推
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874925
Longfei Bai
{"title":"Bathtub Extrapolation of IBIS-AMI Timing Jitter","authors":"Longfei Bai","doi":"10.1109/SPI54345.2022.9874925","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874925","url":null,"abstract":"IBIS Algorithmic Modeling Interface (IBIS-AMI) is widely accepted in the industry to model the analog and algorithmic part of a Serializer/Deserializer (SerDes) PHY. The simulation workflow of IBIS-AMI including deterministic jitter (DJ) and random jitter (RJ) effects is introduced. Dual-Dirac model is used to extrapolate the bathtub to obtain the eye width at a low bit error rate (BER), and its accuracy are validated by comparing to the convolution results of DJ and RJ.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Board-Level Power Integrity Analysis for Complex High-Speed Printed Circuit Boards 复杂高速印刷电路板的板级功率完整性分析
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874933
Kamran Kamran, Gul Shahzad, M. Rizwan Mughal, Fayyaz Ahmed, B. Khan
{"title":"Board-Level Power Integrity Analysis for Complex High-Speed Printed Circuit Boards","authors":"Kamran Kamran, Gul Shahzad, M. Rizwan Mughal, Fayyaz Ahmed, B. Khan","doi":"10.1109/SPI54345.2022.9874933","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874933","url":null,"abstract":"With the increasing speed and complexity of high-performance printed circuit boards, designing a robust Power Delivery Network (PDN) has become the inevitable requirement for the stable and reliable operation of high-speed electronics. On the contrary, poorly designed PDN not only cause various signal integrity (SI) issues but also intensify Conducted and Radiated Emissions (CE & RE) failing EMC compliance at later stages of product design. Therefore, it is pertinent to identify and mitigate potential board-level power integrity (PI) issues before fabrication to prevent iterative hardware prototyping and testing after fabrication. In this work, post-layout PI analysis and optimization flow is presented for a complex high-speed FPGA based data processing board. The analysis is performed in the frequency domain (FD) using the industry's proven electromagnetic (EM) solver tools, while FD data is imported back in the time domain (TD) to assess and improve the transient response of signal switching noise (SSN).","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130490413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DDR interface modeling and chip decoupling capacitance optimization through jitter simulation 通过抖动仿真实现DDR接口建模和芯片去耦电容优化
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874934
Marie Peyrard, Dominique Marais, Xavier Duperthuy, N. Froidevaux, Gilles Jacquemod
{"title":"DDR interface modeling and chip decoupling capacitance optimization through jitter simulation","authors":"Marie Peyrard, Dominique Marais, Xavier Duperthuy, N. Froidevaux, Gilles Jacquemod","doi":"10.1109/SPI54345.2022.9874934","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874934","url":null,"abstract":"This paper presents the optimization of additional chip decoupling capacitance, to reduce the noise induced jitter of a DDR interface. This contribution to periodic jitter affects the power distribution network (PDN) design and must be anticipated through system modeling and simulations. A new PDN chip model comprising the equivalent resistance between power pads is introduced. Using this model, the methodology presented allows to select the appropriate number of chip decoupling capacitance to get an operational interface, through noise induced jitter simulation.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Signal Integrity Assessment of External ESD Protection for Gbit/s Data Rates on Ceramic Test Fixture 陶瓷测试夹具gb /s数据速率下的外部ESD保护信号完整性评估
2022 IEEE 26th Workshop on Signal and Power Integrity (SPI) Pub Date : 2022-05-22 DOI: 10.1109/SPI54345.2022.9874937
T. Wendt, Cheng Yang, C. Schuster, Jose Enrique Hernandez, Jennifer Schütt
{"title":"Signal Integrity Assessment of External ESD Protection for Gbit/s Data Rates on Ceramic Test Fixture","authors":"T. Wendt, Cheng Yang, C. Schuster, Jose Enrique Hernandez, Jennifer Schütt","doi":"10.1109/SPI54345.2022.9874937","DOIUrl":"https://doi.org/10.1109/SPI54345.2022.9874937","url":null,"abstract":"In order to reduce the strain of ESD events on the internal ESD protection of I/O buffers, external ESD protection is deployed in form of standalone chips soldered on the signal trace on the ceramic. These elements introduce parasitics which need to be minimized or compensated in order to limit the degradation of signal integrity. This paper investigates the signal integrity performance of a standalone ESD protection device for multi Gbit/s data rates including nonlinear junction capacitance due to the ESD protection diode. Good model to hardware correlation is demonstrated by comparing simulation results with measurements up to 40 GHz. The results show that the nonlinear junction capacitance can be approximated as linear for the investigated cases.","PeriodicalId":285253,"journal":{"name":"2022 IEEE 26th Workshop on Signal and Power Integrity (SPI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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