DDR interface modeling and chip decoupling capacitance optimization through jitter simulation

Abstract

This paper presents the optimization of additional chip decoupling capacitance, to reduce the noise induced jitter of a DDR interface. This contribution to periodic jitter affects the power distribution network (PDN) design and must be anticipated through system modeling and simulations. A new PDN chip model comprising the equivalent resistance between power pads is introduced. Using this model, the methodology presented allows to select the appropriate number of chip decoupling capacitance to get an operational interface, through noise induced jitter simulation.