Board-Level Power Integrity Analysis for Complex High-Speed Printed Circuit Boards

Abstract

With the increasing speed and complexity of high-performance printed circuit boards, designing a robust Power Delivery Network (PDN) has become the inevitable requirement for the stable and reliable operation of high-speed electronics. On the contrary, poorly designed PDN not only cause various signal integrity (SI) issues but also intensify Conducted and Radiated Emissions (CE & RE) failing EMC compliance at later stages of product design. Therefore, it is pertinent to identify and mitigate potential board-level power integrity (PI) issues before fabrication to prevent iterative hardware prototyping and testing after fabrication. In this work, post-layout PI analysis and optimization flow is presented for a complex high-speed FPGA based data processing board. The analysis is performed in the frequency domain (FD) using the industry's proven electromagnetic (EM) solver tools, while FD data is imported back in the time domain (TD) to assess and improve the transient response of signal switching noise (SSN).