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2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)最新文献

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Yield and Scaling Improvements in Next-Generation 2.5 THz SLCFET Devices to Enable Ultra-wideband DC-110GHz Switch MMICs 下一代2.5 THz SLCFET器件的良率和缩放改进，以支持超宽带DC-110GHz开关mmic
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682468
J. Mlack, Nick Edwards, Brian Novak, Annaliese Drechsler, Jordan Merkel, T. Vasen, D. Hannan, P. Brabant, I. Wathuthanthri, J. Parke, S. Wanis, R. Howell, Ken A. Nagamatsu
{"title":"Yield and Scaling Improvements in Next-Generation 2.5 THz SLCFET Devices to Enable Ultra-wideband DC-110GHz Switch MMICs","authors":"J. Mlack, Nick Edwards, Brian Novak, Annaliese Drechsler, Jordan Merkel, T. Vasen, D. Hannan, P. Brabant, I. Wathuthanthri, J. Parke, S. Wanis, R. Howell, Ken A. Nagamatsu","doi":"10.1109/BCICTS50416.2021.9682468","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682468","url":null,"abstract":"This paper reports improvements in the Superlattice Castellated Field Effect Transistor (SLCFET) 10-channel device process to enable fabrication of ultra-wideband DC-110GHz Single Pole Double and Triple Throw (SPDT/SP3T) MMICs. The 10-channel SLCFET device offers higher performance, but is more difficult to fabricate. Through planarization of the device contact pads, the fabrication of the gate electrode is improved, thereby improving DC yield for the devices by more than 50%. Additionally, the planarization has enabled the scaling of the device source/drain spacing to 64% of baseline devices while maintaining a greater than 50% DC yield. The decrease in the source/drain spacing reduces on-resistance while minimally impacting the off-capacitance, leading to a higher achievable switch Figure of Merit Fco >3THz. The improved FET designs demonstrated improved insertion loss in the wideband SPDT and SP3T MMICs while showing no change in isolation. These ultra-wideband MMICs offer better insertion loss and bandwidth than is possible from other conventional technologies.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"51 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Novel Method to Determine Transistor Geometry for PA Design 一种确定放大器晶体管几何形状的新方法
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682478
Yingying Yang, Bin Li, Brian Johnson, Hal Banbrook
{"title":"A Novel Method to Determine Transistor Geometry for PA Design","authors":"Yingying Yang, Bin Li, Brian Johnson, Hal Banbrook","doi":"10.1109/BCICTS50416.2021.9682478","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682478","url":null,"abstract":"This method uses a new concept “Gain Number <tex>${left( {GN} right)}$</tex>” and “Transition Frequency <tex>${left( {f_{Tr}} right)}$</tex>” (between Maximum Stable Gain <tex>${left( {MSG} right)}$</tex> and Maximum Available Gain <tex>$left. {left( {MAG} right)} right)$</tex> as figures-of-merit to select a most suitable HBT device for a PA design of a certain required frequency <tex>${left( {f _ dsn} right)}$</tex>. The key is to establish relationships between <tex>${GN}$</tex> and <tex>${f_Tr}$</tex>, and the HBT's geometrical parameters and associated mathematical quantities: the ratio of an HBT's base pedestal area <tex>$left. {left( {A_B} right)} right)$</tex> to emitter area <tex>$left. {left( {A_E} right)} right)$</tex> and the product of base resistance <tex>$left. {left( {R_B} right)} right)$</tex> and <tex>${A_E}$</tex>.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134592547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
100-300GHz Wireless: ICs, Arrays, and Systems 100-300GHz无线:集成电路，阵列和系统
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682212
M. Rodwell, A. Farid, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh
{"title":"100-300GHz Wireless: ICs, Arrays, and Systems","authors":"M. Rodwell, A. Farid, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh","doi":"10.1109/BCICTS50416.2021.9682212","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682212","url":null,"abstract":"100–300GHz wireless systems can provide very high data rates per signal beam, and, given the short wavelengths, even compact arrays can contain many elements, and hence can simultaneously transmit, in the same frequency band, many simultaneous independent signal beams to further greatly increase capacity. We will describe representative system designs, including wireless hubs and wireless backhaul links using massive spatial multiplexing, plus imaging radar systems, evaluate their feasible performance, and identify the key challenges in implementation, including transistor and IC performance, array physical design, digital beam former complexity, and systems cost.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
RF LDMOS Transistor Plastic Immunity Enhancement in Power Amplifier Module for 5G Applications 5G应用中射频LDMOS晶体管抗扰度增强
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682465
Vikas S. Shilimkar, Kevin Kim
{"title":"RF LDMOS Transistor Plastic Immunity Enhancement in Power Amplifier Module for 5G Applications","authors":"Vikas S. Shilimkar, Kevin Kim","doi":"10.1109/BCICTS50416.2021.9682465","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682465","url":null,"abstract":"Plastic encapsulation is one of the most common processes in packaging of RF products. It is critical to understand and mitigate the impact of plastic on circuit performance. In this paper, we show that plastic encapsulation increases an LDMOS transistor gate, drain, and gate-drain capacitances by about 3%, 15%, and 45%, respectively. This translates to degradation of power gain, and shifts and rotations in load-pull contours. In addition, losses in the plastic material cause the transistor efficiency to degrade as well. We show two techniques to address the challenges caused by plastic encapsulation. First, an additional die coat is proposed. Second, a novel extended shield between gate and drain metallization is demonstrated. The additional die coat results in improved performance, which is achieved with negligible change to the load-pull contour despite the plastic encapsulation. The extended shield mitigates the increase in gate, drain, and gate-drain capacitances that otherwise result from plastic encapsulation. This is reflected in the large-signal performance, with gain improved by 1.6 dB and efficiency enhanced by almost 2 % points.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126168564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Gain 500-GHz InP HBT Power Amplifiers 高增益500ghz InP HBT功率放大器
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682464
J. Cheron, Rob D. Jones, R. Chamberlin, Dylan F. Williams, M. Urteaga, Kassiopeia A. Smith, N. Jungwirth, B. Bosworth, C. Long, N. Orloff, P. Aaen, A. Feldman
{"title":"High-Gain 500-GHz InP HBT Power Amplifiers","authors":"J. Cheron, Rob D. Jones, R. Chamberlin, Dylan F. Williams, M. Urteaga, Kassiopeia A. Smith, N. Jungwirth, B. Bosworth, C. Long, N. Orloff, P. Aaen, A. Feldman","doi":"10.1109/BCICTS50416.2021.9682464","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682464","url":null,"abstract":"We report two terahertz monolithic integrated circuit (TMIC) amplifiers operating at 500 GHz. The 6-stage single-ended power amplifiers use Teledyne's 130 nm indium-phosphide double heterojunction bipolar transistors in a common-base configuration. The impedance matching networks of the first amplifier are designed with shunt lines while the second amplifier uses shunt metal-insulator-metal capacitors. We measured and compared the small-signal and large-signal performance of the two amplifiers around 500 GHz. Although the two TMICs exhibit a similar transducer gain (24 dB) and output power (up to −0.7 dBm), we obtained better yield with the amplifiers designed with shunt lines.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock 模拟解复用器工作速度高达200gs /s，使用四个时间交错开关发射器跟随器，占空比为50%
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682471
P. Thomas, M. Grözing, M. Berroth
{"title":"Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock","authors":"P. Thomas, M. Grözing, M. Berroth","doi":"10.1109/BCICTS50416.2021.9682471","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682471","url":null,"abstract":"This paper presents the design and experimental results of a voltage mode analog demultiplexer (ADeMUX) that uses four time interleaved switched emitter follower track-and-hold (T/H) circuits. The preamplifiers and sampling cores are linearized for ultra-broadband operation. With the utilized 90-nm SiGe-BiCMOS technology offering 300 GHz fT and 480 GHz fmax, we are able to operate the ADeMUX with up to 4 x 50 GS/s = 200 GS/s - the highest reported sampling rate to date. Compared with the state-of-the-art current mode ADeMUX circuits, the presented device offers an increase in sampling rate of more than 50%. At 128 GS/s, the chip shows the highest input bandwidth of more than 50 GHz and a linearity of more than 3 bit. This ultra-broadband analog time interleaver can be used to feed four analog-to-digital converters in CMOS technology, due to the reduced bandwidth requirement of only 16 GHz for operation at 128 GS/s or 25 GHz for 200 GS/s.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128837096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Thermal Resistance Formulation and Analysis of III-V FETs Based on DC Electrical Data 基于直流电学数据的III-V型场效应管热阻公式及分析
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682211
D. Root, Jianjun Xu, M. Iwamoto
{"title":"Thermal Resistance Formulation and Analysis of III-V FETs Based on DC Electrical Data","authors":"D. Root, Jianjun Xu, M. Iwamoto","doi":"10.1109/BCICTS50416.2021.9682211","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682211","url":null,"abstract":"This paper presents a unified framework for estimating the thermal resistance of a FET from DC drain current data. A mathematical derivation from physical principles is presented for a recently introduced practical expression for thermal resistance that is obtained from easily acquired DC data. Limitations of this expression are identified and circumvented by extending the formalism with a partial differential equation for temperature-dependent thermal resistance. This partial differential equation for thermal resistance is solved by numerical analysis of bias-dependent DC data versus temperature using the adjoint artificial neural network training procedure. Results applied to measured data from GaAs and GaN FET technologies demonstrate that the proposed method enables predictions (estimates) over a wide range of device operating conditions in bias and temperature.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electro-Thermal and Trapping Characterization of AlGaN/GaN RF Power HEMTs AlGaN/GaN射频功率hemt的电热及俘获特性
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682206
J. Pedro, João L. Gomes, L. Nunes
{"title":"Electro-Thermal and Trapping Characterization of AlGaN/GaN RF Power HEMTs","authors":"J. Pedro, João L. Gomes, L. Nunes","doi":"10.1109/BCICTS50416.2021.9682206","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682206","url":null,"abstract":"Because the predictions of all types of AlGaN/GaN RF power HEMT device behavior, such as trapping and electro-thermal phenomena, are essential to develop CAD/CAE platforms useful for RF circuit design, this paper discusses some recent advances on device characterization techniques necessary to build accurate nonlinear equivalent-circuit models of this transistor technology. For that, a measurement methodology and instrumentation needed to guarantee isodynamic pulsed dc I/V characteristics and pulsed S-parameters is presented, and exemplifying results are shown.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133172950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral Branch Offset Currents 使用静态和调制的积分支路偏置电流增强频率采集范围的无参考Bang-bang CDR
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682207
Mohammed Iftekhar, Sergiy Gudyriev, C. Scheytt
{"title":"Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral Branch Offset Currents","authors":"Mohammed Iftekhar, Sergiy Gudyriev, C. Scheytt","doi":"10.1109/BCICTS50416.2021.9682207","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682207","url":null,"abstract":"This paper presents a technique to extend the frequency acquisition range for bang-bang phase-detector-based clock and data recovery (CDR) circuits without an additional frequency acquisition loop or lock detection circuit. The per-manent modulation of the offset current in the CDR's integral branch enhances the acquisition range by nearly 4 times, covering the entire tuning range of the voltage controlled oscillator. The increase in power dissipation and the chip area are negligible. This technique was implemented and measured in a 28 Gbps NRZ bang-bang CDR chip to confirm the working principle. In addition to the increased acquisition range, the CDR also surpasses jitter related specifications from the OIF CEI-28G-VSR standard.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimized Buffer Stack with Carbon-Doping for Performance Improvement of GaN HEMTs 碳掺杂优化缓冲层以提高GaN hemt的性能
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI: 10.1109/BCICTS50416.2021.9682203
Ajay Shanbhag, P. SruthiM., F. Medjdoub, A. Chakravorty, N. Dasgupta, A. DasGupta
{"title":"Optimized Buffer Stack with Carbon-Doping for Performance Improvement of GaN HEMTs","authors":"Ajay Shanbhag, P. SruthiM., F. Medjdoub, A. Chakravorty, N. Dasgupta, A. DasGupta","doi":"10.1109/BCICTS50416.2021.9682203","DOIUrl":"https://doi.org/10.1109/BCICTS50416.2021.9682203","url":null,"abstract":"This paper focuses on determining an optimized value of carbon-doping level in the buffer and corresponding channel thickness to improve the performance of GaN HEMTs in terms of subthreshold slope $(SS)$, breakdown voltage $(V_{BD})$ and transit frequency $(f_{t})$. With the increase in carbon-doping, we observe improvements in $SS$ and $V_{BD}$ while the $f_{t}$ is reduced. However, as the channel thickness increases above a certain thickness, no significant impact of carbon-doping is observed on the characteristics. TCAD simulation is calibrated using experimental data for a device with carbon-doping level of $3times 10^{18}cm^{-3}$ in the buffer with channel thickness of 500 nm. Using the calibrated device in TCAD, the carbon-doping level and channel thickness are varied to see the effects on different parameters. We observed that an optimized channel thickness of 200 nm with carbon-doping level of $1times 10^{19}cm^{-3}$ in the buffer yields the best results in terms of $V_{BD}$ and $f_{t}$.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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