Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)最新文献

{"title":"Two dimensional optical data links","authors":"R. A. Novotny, M. J. Wojcik, M. G. Beckman, S. J. Hinterlong, A. Lentine","doi":"10.1109/ECTC.1993.346759","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346759","url":null,"abstract":"The complexity and size of interconnection rich telephone switching systems requires the extension of data buses over a large complement of frames. Physical designers have chosen bit serial transport over fiber to overcome the limitations of coax. It has been shown that for certain optical data link applications there exists an optimum degree of parallelism (based on cost) depending on the data rate and the number of the channels. Prototype One Dimensional Optical Data Links (1D-ODL) using linear 1/spl times/n device arrays, have been demonstrated in a number of laboratories, taking advantage of the current infrastructure of fiber ribbon, splices, and connectors. Extending this concept to a second dimension creating a Two Dimensional Optical Data Link (2D-ODL) using n/spl times/m device arrays, may yield further economies of scale. We have constructed several prototype 2D-ODLs using direct modulation of 2D arrays of Vertical Cavity Surface Emitting Laser's (VCSELs), and Symmetric Self-Electrooptic Effect Device (S-SEED) reflection modulators with Silicon p-i-n/bipolar OEIC receivers. Most recently we studied a 4/spl times/18 2D-ODL using S-SEED reflection modulators and FET-SEED OEIC receiver arrays. 2D-ODL system demonstrations to date are described, and benefits and drawbacks of each technology are discussed.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115402102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rigorous electromagnetic modeling of chip-to-package (first-level) interconnections","authors":"Yuh-sheng Tsuei, A. Cangellaris, J. Prince","doi":"10.1109/ECTC.1993.346784","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346784","url":null,"abstract":"A methodology is presented for the rigorous electromagnetic analysis of pulse transmission through first-level interconnects. The methodology combines a full-wave, vectorial, time-dependent Maxwell's equations solver with SPICE circuit models for the nonlinear drivers, to facilitate the accurate modeling of the electromagnetic phenomena occurring at the chip-to-package interface. Comparisons of the results obtained using this method with others calculated using SPICE simulations are used to validate the method and demonstrate its application in the electromagnetic modeling of high-speed packaging structures.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124965332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compliance metric for the S-bend lead design for surface mount components, with application to clip-leads","authors":"R. Kotlowitz, I.M. Nevarez","doi":"10.1109/ECTC.1993.346696","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346696","url":null,"abstract":"New stiffness metrics have been developed from an upgraded S-lead structural model that extends compliance evaluation capabilities to a wide variety of commercial S-lead designs. By selectively eliminating lead members, the generalized S-lead structural model can be used to represent a broad range of common lead forms for SM (surface mount) components. The S-lead directional spring constants are given in an easy-to-apply, algebraic format suitable for computer and spread-sheet evaluation. Compliance evaluation has been performed for a commercial S-bend clip-lead specifically developed for high-reliability SM interconnection of CCCs (ceramic chip carriers) on organic circuit-boards. Accelerated powered cycling of clip-leaded CCCs on epoxy-glass circuit-boards has shown that leads with diagonal stiffness in the nominal range of 10-40 lb/in provide a comparatively high margin for SM attachment reliability. The diagonal stiffness of S-bend lead designs can be tailored by using the upgraded compliance formulation to optimize the contour and critical dimensions.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123185663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance pump laser modules for erbium-doped fiber amplifiers","authors":"S. Huang, L. A. Greenberg, T.A. Corser","doi":"10.1109/ECTC.1993.346736","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346736","url":null,"abstract":"A 14-pin butterfly pump laser module for erbium-doped fiber amplifiers is described. A high coupling microlens has been realized by etching. A coupling efficiency of 74% has been measured for 1.48-/spl mu/m pump lasers with a variety of far-field angles. The etched microlens is fabricated by batch process and is highly manufacturable. This microlens also provides less reflection and thus interferes less with the operation of lasers. A /spl Delta/T of 60/spl deg/C was measured for an anticipated end-of-life laser chip power dissipation of 1.2 W. The observed performance degradation after a variety of thermal and mechanical shocks is found to be negligible. A maximum change of 5% in coupling efficiency was measured after 2000 hr of 85/spl deg/C bake. The TEC (thermoelectric cooler) resistance measurement showed negligible change, Less than 0.2 dB of temperature tracking error was observed from the routine fabrication data.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lead-on-chip technology for high performance packaging","authors":"M. Lamson, D. Edwards, S. Groothius, G. Heinen","doi":"10.1109/ECTC.1993.346723","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346723","url":null,"abstract":"The modeling and simulation efforts for the development of a lead-over-chip (LOC) style package for 16 Mb dynamic random access memories is described. Electrical models and simulation address the effects of power bus noise and the interaction of chip conductors with the LOC lead frame. The thermomechanical stress issues in the LOC package are modeled using finite element techniques to optimize the design and material properties to avoid damage to the chip or package during fabrication and testing. For surface mount components, stress from the reflow process resulting from vapor pressure concentrated at points of delamination must also be comprehended and minimized. Thermal analysis of the LOC package was performed using finite element analysis and measurements, and the data were compared to those of standard packaging designs.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127576907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvements in index alignment method for laser-fiber array packaging","authors":"M.S. Cohen, M. DeFranza, F. J. Canora, M. Cina, R. A. Rand, P. Hoh","doi":"10.1109/ECTC.1993.346756","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346756","url":null,"abstract":"An \"index alignment\" method, based on the registration of fiducial marks, was previously developed for passive alignment of a laser array to a corresponding fiber array. This method has recently been improved and used to fabricate laser-fiber array transmitter modules for single-mode operation at 1300 nm. An improved computer-controlled alignment-stage system with machine-vision features has been installed in order to render the alignment procedure faster, more precise, and more reliable; this system was particularly effective in quick achievement of the difficult but necessary angular alignment of the components. Special \"self-registration\" component-fabrication techniques were also developed to avoid mask-registration errors associated with the fabrication of the laser chip and the fiber carrier, so that the fiducial marks were automatically keyed to the positions of the laser ridges and V grooves, respectively. Measures were also taken to improve the accuracy of alignment of the etch mask to the silicon crystallographic axes during fiber-carrier fabrication, and to improve the etch-stop indication process. These techniques permitted an estimated accuracy and wafer-scale uniformity of /spl sim//spl plusmn/0.5 /spl mu/m of the fiber-carrier V-groove widths. In addition, the essential elements of of a practical technique for separation of a large-array laser-fiber module into a multiplicity of small-array submodules was demonstrated; in this way the cost of the alignment procedure could be amortized over a large number of transmitter modules. Several connectorized laser-fiber array modules were fabricated with the improved alignment apparatus and components. Test results showed that for single-mode operation at 1300 nm, coupling efficiencies greater than 8% could be achieved for a laser-fiber spacing of about 35 /spl mu/m. Such values closely approach the 9% coupling efficiency observed at this spacing with active alignment. Tests of the completed module at 1 Gb/s showed values of RIN low enough to permit operation at distances of about 1 km.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129945361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 820 pin PGA for ultra large-scale BiCMOS devices","authors":"Y. Hiruta, N. Hirano, K. Itoh, Y. Yamaji, K. Kato, Y. Motoyama, J. Ohno, R. Homma, S. Kojima, T. Sudo","doi":"10.1109/ECTC.1993.346816","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346816","url":null,"abstract":"A high pin count, high performance PGA has been developed for next-generation ASIC devices which apply half-micron BiCMOS technology and have a maximum usable gate count of 300 K. In view of the advances in CMOS and BiCMOS ULSI technologies, high performance packages are required. This new package has been designed with due consideration of all package functions. Packages for high-end devices need to satisfy the following requirements: high electrical performance, low thermal resistance and high pin count in keeping with easy routing of PWB. The body size of the developed package is 60/spl times/60 mm/sup 2/. Surface mount type pin joint was adopted to realize high wiring density of a printed wiring board. This package has 820 pins with 50 mil pitch, and 5 rows. A small pin diameter of 0.2 mm and a short pin length of 3.0 mm were used for surface mounting.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126795265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Featured elastomer design for connector applications","authors":"W. Brodsky, A. Knight, T. Macek","doi":"10.1109/ECTC.1993.346805","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346805","url":null,"abstract":"This paper discusses a molded elastomeric structure that has been developed for use in connector applications. With the use of elastomeric materials, several challenges occur such as: dimensional stability for a grid of contacts as the elastomer member is compressed; contact force distribution across a grid of electrical contacts supported by a homogeneous molded elastomeric member constrained by boundary conditions; compressive stiffness of the elastomer and its ability to accommodate actuation tolerances within a contact force range; and structural stability of slender elastomeric features when used to increase the elastomeric structures compliancy. As connector I/O and densities increase, use of elastomeric materials with flexible circuits to replace metallic spring and conductor combinations is increasing. One advantage of this combination is the ability to arrange the contacts into dense arrays. In addition to the physical geometry, the component set offers several advantages to the electrical designer, dielectric constant, characteristic impedance, etc.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125801715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High density integrated circuit design: simultaneous switching ground/power noises calculation for pin grid array packages","authors":"M. Bedouani","doi":"10.1109/ECTC.1993.346724","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346724","url":null,"abstract":"The author presents basic electrical models to calculate equivalent inductances (noises) for a 179 pin grid array package as a function of ground/power/signals pin organizations. A full experimental inductances measurement based on time domain reflectometry and frequency method is also presented. A specific test vehicle was elaborated to avoid fixturing noise. Calculated and measured signal effective inductance values are compared. Each integrated circuit logic family has a specific switching point. Thus, adequate ground/power/signal organization depends on the technology used. For some logic families like TTL (transistor transistor logic) and DCFL in silicon and GaAs technologies, the switching point near the ground voltage indicates that the critical path is ground. On other hand, the internal switching current becomes comparable to the input buffers (30-50 mA/ns). Thus, the ground/signal/power organization of output buffers must take into account the internal logic I/O's (input/outputs). The noises are as function of the number of IO buffers and internal logic IO gates.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predicting solder joint reliability, model validation","authors":"R. Iannuzzelli","doi":"10.1109/ECTC.1993.346684","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346684","url":null,"abstract":"A reliability predictive technique is presented using a commercially available finite element code and previously developed material properties for eutectic tin-lead solder. The predictive model is validated for three types of surface mount solder joints, i.e., 50 mil gull, 25 mil gull, and 50 mil-butt leaded joints and also a 100 mil intrusive leaded joint using a combination of crack length and \"Mechanical Strength Degradation\" which is a metric developed at Digital. An accelerated thermal cycle is used to expedite the qualification and validation process. This technique can also be applied to leadless (bump) SMT joints.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126988997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}