Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)最新文献

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Polyimides with reduced dielectric anisotropy 降低介电各向异性的聚酰亚胺
J. W. Labadie, H. Lee, D. Boese, D. Yoon, W. Volksen, P. Brock, Y. Cheng, M. Ree, K.R. Chen
{"title":"Polyimides with reduced dielectric anisotropy","authors":"J. W. Labadie, H. Lee, D. Boese, D. Yoon, W. Volksen, P. Brock, Y. Cheng, M. Ree, K.R. Chen","doi":"10.1109/ECTC.1993.346825","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346825","url":null,"abstract":"Ordered polyimides have been the subject of considerable interest for thin film applications due to their excellent balance of final properties, however, these polyimides have been shown to have an exceptionally large dielectric anisotropy. Two approaches were examined as a means of obtaining materials with lowered dielectric anisotropies. ATR spectroscopy was used to measure in-plane and out-of-plane refractive indices from which the directional dielectric constant was estimated. In one case, monomers based on hexafluoroisopropylidine were introduced into PMDA at levels /spl les/20 mole%. This afforded some reduction in the in-plane dielectric constant. A more promising approach involved the use of polyimides derived from 2,2'-bis(trifluoromethyl)benzidine (BTFB). The PMDA-BTFB polyimide displayed the best combination of properties, including an estimated in-plane dielectric constant of 2.9 and an out-of-plane dielectric constant of 2.6 at 1 MHz.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129244407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Attachment reliability evaluation and failure analysis of thin small outline packages (TSOPs) 薄型小外形封装附件可靠性评估与失效分析
D. Noctor, F. Bader, A. Viera, P. Boysan, S. Golwalkar, D. Foehringer
{"title":"Attachment reliability evaluation and failure analysis of thin small outline packages (TSOPs)","authors":"D. Noctor, F. Bader, A. Viera, P. Boysan, S. Golwalkar, D. Foehringer","doi":"10.1109/ECTC.1993.346853","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346853","url":null,"abstract":"This paper describes a series of studies to evaluate the long term surface mount attachment reliability of TSOPs using thermal cycling as an acceleration method. Visual inspections, pull strength, and scanning electron microscopy were used to characterize the solder joints. In addition, the solder plating, lead wetting and aging characteristics were evaluated. Failure during thermal cycling was primarily caused by the coefficient of thermal expansion (CTE) mismatch between the package and the printed wiring board. Using acceleration factors based on solder joint strain energies induced by global and local mismatches during thermal cycling, the experimental results are extrapolated to various use conditions and life expectancies. The TSOP solder joint reliability depends on environmental conditions (cyclic temperature range, temperature maximum and dwell time), board thickness and materials, product intended service life and expected hazard rate limits.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132539852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The impact of materials on the flammability of printed wiring board products 材料对印制板产品易燃性的影响
W. R. Lambert
{"title":"The impact of materials on the flammability of printed wiring board products","authors":"W. R. Lambert","doi":"10.1109/ECTC.1993.346843","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346843","url":null,"abstract":"Despite the fact that appropriate design precautions and materials selection procedures are implemented to ensure the safety of printed circuit board equipment, fires, though rare, can and do occur. Design and manufacture for ultimate product safety reflects the fundamental aspects of the quality process and minimization of the potential for fire during failure requires a high level of appreciation for how design, materials and manufacturing combine to determine product reliability. It is therefore important that equipment designers, manufacturers and component vendors understand the general mechanisms of fires in printed wiring board (PWB) products and further determine how circuit design and materials selection impact the flammability of PWB products. In this paper the author reviews the impact which printed circuit board laminates, solder masks and design rules have on the initiation and propagation of fires in electronic equipment as derived from experimental observations. General recommendations for minimizing the potential for fires in electronic equipment are presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130887927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Transmission line analysis of MCM interconnects MCM互连的传输线分析
E. Beyne, J. Peeters
{"title":"Transmission line analysis of MCM interconnects","authors":"E. Beyne, J. Peeters","doi":"10.1109/ECTC.1993.346726","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346726","url":null,"abstract":"The transmission line behavior of MCM-D interconnection lines is discussed with particular emphasis on the frequency dependent loss and delay characteristics. A broadband model covering the frequency spectrum from DC to RF is proposed. The applicability of this model is experimentally verified by comparison with measured S-parameters from 45 MHz to 18 GHz on test structures realized with two different MCM-D technologies. The broadband model is integrated in the time-domain network simulator TRANSPLUS. This program was developed for the simulation of the interconnection circuitry between chips, it thus includes models for the output circuits of the chips, the packaging, and the (coupled) interconnection lines. Simulations of different MCM-D interconnections between CMOS and bipolar chips are discussed.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131133961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accelerated life test of z-axis conductive adhesives z轴导电胶粘剂加速寿命试验
D. D. Chang, J. Fulton, H. Ling, M. Schmidt, R. Sinitski, C. Wong
{"title":"Accelerated life test of z-axis conductive adhesives","authors":"D. D. Chang, J. Fulton, H. Ling, M. Schmidt, R. Sinitski, C. Wong","doi":"10.1109/ECTC.1993.346717","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346717","url":null,"abstract":"Conductive-particles filled adhesives have been widely used for flex-to-rigid board interconnections in many consumer electronics applications, such as calculators and palmcorders. Most of the applications were in coarse pitch interconnections where the adjacent conductor's distance is greater than 10 mil. The success of coarse pitch applications has increased the interest to use such adhesives in fine pitch applications, such as flip-chip on board interconnection. Since these materials contain metallic particles to conduct currents in the z-direction (i.e. perpendicular to the plane of circuit board), their propensity for metal migration is a concern. Therefore we have applied accelerated temperature, humidity and bias (THB) tests to a group of materials designed for fine pitch applications. Our studies include two phases. Phase-I focused on the high voltage (100 V) THB test and the associated conduction and failure mechanisms. Phase-II evaluates the time-to-fail under medium (50 V) and low voltage (10 V) THB conditions. The results of Phase-I studies showed significant metal migration in our tests, and we proposed enhanced electric field stresses (10/sup 4/ to 10/sup 5/ V/cm) as the driving force for failures.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125433025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Crystallization of vitreous seal in hermetic packages 玻璃体密封在密封包装中的结晶
R.O. Pantaleon, M. Mena
{"title":"Crystallization of vitreous seal in hermetic packages","authors":"R.O. Pantaleon, M. Mena","doi":"10.1109/ECTC.1993.346819","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346819","url":null,"abstract":"Dull glass in ceramic packages which leads to electrical bridging between leads of tin plated parts has been identified to be due to the formation of metallic lead crystals on the solder glass surface. Controlled sealing atmosphere testing revealed that the presence of small amounts of carbon and hydrogen-containing solvents in the sealing furnace results in the formation of metallic lead crystals. The lead crystals may be dissolved with nitric acid prior to tin plating to eliminate bridging. The glass dissolution in nitric acid is described by the equation: /spl utri/W (mg/inch square)=23[H/sup +/] exp(-0.4/RT)t. Two other types of crystals, columnar lead oxide and acicular hydrocerrusite are also formed on the solder glass surface but they do not impact the reliability of the package.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123188838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CD laser optical data links for workstations and midrange computers 用于工作站和中型计算机的CD激光光学数据链路
R. Soderstrom, S. J. Baumgartner, B. Beukema, T. R. Block, D. Karst
{"title":"CD laser optical data links for workstations and midrange computers","authors":"R. Soderstrom, S. J. Baumgartner, B. Beukema, T. R. Block, D. Karst","doi":"10.1109/ECTC.1993.346798","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346798","url":null,"abstract":"The Optical Link Card (OLC) is a high speed fiber optic data link developed for low cost computer interconnect applications. Several versions of this OLC family are now in volume production. They incorporate a short-wavelength, CD-type laser source, high-density surface mount (SMT) packaging, and a novel technique to comply with worldwide laser safety regulations. The current cards, operating at 220 Mb/s and 266 Mb/s over 2 km of multimode optical fiber, provide compatibility with the emerging ANSI standard called Fiber Channel. Future extensions, especially to higher data rates, are being developed to meet the computer user's growing demand for higher bandwidth networking solutions.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A silicon-on-silicon packaging technology for advanced ULSI chips 一种用于先进ULSI芯片的硅对硅封装技术
T. Kousaka, N. Senba, A. Nishizawa, N. Takahashi, T. Shimoto, T. Koike
{"title":"A silicon-on-silicon packaging technology for advanced ULSI chips","authors":"T. Kousaka, N. Senba, A. Nishizawa, N. Takahashi, T. Shimoto, T. Koike","doi":"10.1109/ECTC.1993.346740","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346740","url":null,"abstract":"A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Encapsulants used in flip-chip packages 用于倒装芯片封装的密封剂
D. Suryanarayana, T. Wu, J. Varcoe
{"title":"Encapsulants used in flip-chip packages","authors":"D. Suryanarayana, T. Wu, J. Varcoe","doi":"10.1109/ECTC.1993.346720","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346720","url":null,"abstract":"Low thermal expansion encapsulants have been used in a wide range of IBM flip-chip products to enhance the fatigue life of solder interconnections and to prevent environmental attack. In order to determine whether an encapsulant can satisfy all requirements of a given product or process, the physical behaviors of the encapsulant must be carefully characterized. Typical material properties of interest are: viscosity and flow coverage, thermal expansion, modulus, glass transition temperature, filler size, alpha activity, adhesion, ionics content, fracture toughness, and electrical properties. The sensitivity of these properties to process variables such as encapsulant dispensing, gelling, curing and post curing exposures to environment and reliability experiments need to be explored. An overall evaluation of all these properties is essential for determining the ultimate performance of the encapsulant on specific products. This paper presents a systematic approach to quantify these encapsulant properties. Various test methods and their relevant technical aspects are discussed. Results achieved on a few selected materials are also presented as examples.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116658386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 90
Reflow soldering evaluation of lead free solder alloys 无铅焊料合金的回流焊评价
C. Melton
{"title":"Reflow soldering evaluation of lead free solder alloys","authors":"C. Melton","doi":"10.1109/ECTC.1993.346729","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346729","url":null,"abstract":"A quantitative dynamic solder wettability measurement was used to evaluate the effects of reflow processing on the wettability parameters associated with the nonlead bearing solders 96.5% Sn/3.5% Ag and 58% Bi/42% Sn. An experimental design approach employing full factorial experiments was formulated to investigate the solder wetting dependence of the reflow parameters, atmosphere, peak reflow temperature, time above liquidus, and metallization. Solder wettability was determined with respect to the final degree of spread and the extent of solder wetting onto the lands of surface mount components. The solder alloy composition of 96.5% Sn/3.5% Ag was found to exhibit better wetting characteristics than the 58% Bi/42% Sn alloy. This wetting behavior was enhanced under the reflow conditions of a nitrogen atmosphere and the use of a gold metallization. The wetting of the conventional 63% Sn/37% Pb solder alloy was improved over the comparatively processed 58% Bi/42% Sn alloy. However, the 63% Sn/37% Pb solder alloy displayed a greater sensitivity to reflow atmosphere than the 96.5% Sn/3.5% Ag alloy, which generally exhibited better wetting characteristics than the Sn/Pb alloy.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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