一种用于先进ULSI芯片的硅对硅封装技术

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI:10.1109/ECTC.1993.346740

T. Kousaka, N. Senba, A. Nishizawa, N. Takahashi, T. Shimoto, T. Koike

{"title":"一种用于先进ULSI芯片的硅对硅封装技术","authors":"T. Kousaka, N. Senba, A. Nishizawa, N. Takahashi, T. Shimoto, T. Koike","doi":"10.1109/ECTC.1993.346740","DOIUrl":null,"url":null,"abstract":"A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A silicon-on-silicon packaging technology for advanced ULSI chips\",\"authors\":\"T. Kousaka, N. Senba, A. Nishizawa, N. Takahashi, T. Shimoto, T. Koike\",\"doi\":\"10.1109/ECTC.1993.346740\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<<ETX>>\",\"PeriodicalId\":281423,\"journal\":{\"name\":\"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.1993.346740\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1993.346740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

制作了一个用于高性能工作站的精简指令集计算机模块，以证明硅对硅技术的优势和技术可行性。该模块由1个0.8-/spl μ m的CMOS CPU(中央处理器)、1个0.8-/spl μ m的CMOS FPU和6个1.0-/spl μ m的BiCMOS高速缓存组成。这8个芯片连接在一个39/spl × 47 mm平方的硅衬底上，用120 /spl μ m间距的倒装芯片键合直径80 /spl μ m的锡铅凸起。在硅衬底上用20-/spl μ m的线和80-/spl μ m的空间形成高速信号的两层互连。导体为电镀形成的4-/spl μ m厚的金，介质膜为10-/spl μ m厚的聚酰亚胺。在衬底中形成约0.8 nF的去耦电容。通过可靠性和功能测试对该模块进行了评估。可靠性测试包括热循环、功率循环和机械强度测试。通过将模块连接到IBM-PC/IF板并使用测试程序进行功能测试。两次评估都是成功的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A silicon-on-silicon packaging technology for advanced ULSI chips

A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)

自引率

0.00%

发文量