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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)最新文献

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A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel 1/4英寸2M像素CMOS图像传感器，1.75晶体管/像素
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332618
M. Mori, M. Katsuno, S. Kasuga, T. Murata, T. Yamaguchi
{"title":"A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel","authors":"M. Mori, M. Katsuno, S. Kasuga, T. Murata, T. Yamaguchi","doi":"10.1109/ISSCC.2004.1332618","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332618","url":null,"abstract":"A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25/spl mu/m pixel pitch with 25% aperture ratio in a 0.25/spl mu/m IP2M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A small GSM power amplifier module using Si-LDMOS driver MMIC 一种小型GSM功率放大器模块，采用Si-LDMOS驱动MMIC
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332661
T. Shimizu, Y. Nunogawa, T. Furuya, S. Yamada, I. Yoshida, H. Masao
{"title":"A small GSM power amplifier module using Si-LDMOS driver MMIC","authors":"T. Shimizu, Y. Nunogawa, T. Furuya, S. Yamada, I. Yoshida, H. Masao","doi":"10.1109/ISSCC.2004.1332661","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332661","url":null,"abstract":"A small quad-band Si-MOS high power amplifier module with a package size of 8x8 mm/sup 2/ includes a driver MMIC in an LDMOS process and provides a built-in power control loop employing a current sense method. The IC achieves 53% power efficiency at 35dBm output power over the 824 to 915MHz GSM band using a 3.6V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A scalable X86 CPU design for 90 nm process 90nm制程的可扩展X86 CPU设计
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332594
J. Schutz, C. Webb
{"title":"A scalable X86 CPU design for 90 nm process","authors":"J. Schutz, C. Webb","doi":"10.1109/ISSCC.2004.1332594","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332594","url":null,"abstract":"A third generation Pentium/sup /spl reg//4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application 一个1.4 Gb/s的DLL，采用二阶电荷泵方案，具有低相位/占空率误差，用于高速DRAM应用
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332669
Kyu-hyoun Kim, Jung-Bae Lee, Woo-Jin Lee, B. Jeong, G. Cho, Jong-Soo Lee, Gyung-Su Byun, Changhyun Kim, Young-Hyun Jun, Sooin Cho
{"title":"A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application","authors":"Kyu-hyoun Kim, Jung-Bae Lee, Woo-Jin Lee, B. Jeong, G. Cho, Jong-Soo Lee, Gyung-Su Byun, Changhyun Kim, Young-Hyun Jun, Sooin Cho","doi":"10.1109/ISSCC.2004.1332669","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332669","url":null,"abstract":"A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the charge pump, is proposed. It makes the output of the charge pump virtually grounded, to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a speed of 1.4 Gb/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
40Gb/s CMOS distributed amplifier for fiber-optic communication systems 光纤通信系统用40Gb/s CMOS分布式放大器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332801
H. Shigematsu, M. Sato, I. Hirose, F. Brewer, M. Rodwell
{"title":"40Gb/s CMOS distributed amplifier for fiber-optic communication systems","authors":"H. Shigematsu, M. Sato, I. Hirose, F. Brewer, M. Rodwell","doi":"10.1109/ISSCC.2004.1332801","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332801","url":null,"abstract":"This paper describes a 0.18 /spl mu/m CMOS distributed amplifier with optimized source degeneration which achieves a 4 dB gain and 39 GHz bandwidth within 1 dB gain variation.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Protection of audio amplifiers based on temperature measurements in power transistors 基于功率晶体管温度测量的音频放大器保护
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332750
B. Krabbenborg
{"title":"Protection of audio amplifiers based on temperature measurements in power transistors","authors":"B. Krabbenborg","doi":"10.1109/ISSCC.2004.1332750","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332750","url":null,"abstract":"An audio amplifier IC has been realized with protection circuitry based directly upon power-transistor temperature measurements. In contrast to current- or voltage-based measurements, this method gives optimal protection independent of supply voltage (9-28V), load (2-16/spl Omega/ BTL), ambient temperature and heat sinking.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128333779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A digital circuit for a minimum distance search using an asynchronous bubble shift memory 一种使用异步泡移存储器进行最小距离搜索的数字电路
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332815
S. Nakahara, T. Kawata
{"title":"A digital circuit for a minimum distance search using an asynchronous bubble shift memory","authors":"S. Nakahara, T. Kawata","doi":"10.1109/ISSCC.2004.1332815","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332815","url":null,"abstract":"The architecture described allows a fully digital circuit to search for the minimum Hamming distance. It compares favorably with prior approaches in its robustness and short design time. A concentration of asynchronous circuit techniques allows a 35 ns search time of 64 entry/spl times/128 bit data with a 0.13 /spl mu/m 5M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129590463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS 一个150MS/s 8b 71mW时间交错ADC在0.18/spl μ m CMOS
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332692
S. Limotyrakis, S.D. Kulchycki, D. Su, B. Wooley
{"title":"A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS","authors":"S. Limotyrakis, S.D. Kulchycki, D. Su, B. Wooley","doi":"10.1109/ISSCC.2004.1332692","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332692","url":null,"abstract":"This paper presents a 150 MS/s 8 bit time-interleaved ADC which has been built in 0.18 /spl mu/m CMOS. Segmentation of the track-and-hold into separate circuits, driving the 1st stage comparators and two interleaved residue paths, together with signal scaling, results in a 45.4 dB SNDR for an 80 MHz input frequency, while dissipating 71 mW from a 1.8 V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129063474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing 一种DSL客户预置设备调制解调器SoC，具有宽带桥接和路由的扩展范围/速率
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332732
A. Saha, S. Oswal, S. Prasad, J. Kennedy, S. Kumar, B. Datta, A. Sharma, R. Singhal, P. Srikanth, S. Raghu, M. Rajesh, M. Jagadeesha, R. Mohan, F. Mujica, D. Beaudoin, B. Karguth, B. Egr, A. Redfern
{"title":"A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing","authors":"A. Saha, S. Oswal, S. Prasad, J. Kennedy, S. Kumar, B. Datta, A. Sharma, R. Singhal, P. Srikanth, S. Raghu, M. Rajesh, M. Jagadeesha, R. Mohan, F. Mujica, D. Beaudoin, B. Karguth, B. Egr, A. Redfern","doi":"10.1109/ISSCC.2004.1332732","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332732","url":null,"abstract":"A highly-integrated DSL modem for residential gateway applications is described. The chip integrates a C62x based DSL PHY, AFE, line driver and receiver, power management, and broadband controller subsystem. A 0.13/spl mu/m 5M CMOS process is used to implement the 2.3W chip. Supplies are 1.5V for digital and 3.3V for analog subsystems.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132373991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
CMOS image sensor using a floating diffusion driving buried photodiode CMOS图像传感器采用浮动扩散驱动埋地光电二极管
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332619
K. Mabuchi, N. Nakamura, E. Funatsu, T. Abe, T. Umeda, T. Hoshino, R. Suzuki, H. Sumi
{"title":"CMOS image sensor using a floating diffusion driving buried photodiode","authors":"K. Mabuchi, N. Nakamura, E. Funatsu, T. Abe, T. Umeda, T. Hoshino, R. Suzuki, H. Sumi","doi":"10.1109/ISSCC.2004.1332619","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332619","url":null,"abstract":"Two 2.5V VGA CMOS image sensors with 3.45/spl mu/m and 3.1/spl mu/m buried photodiode-pixels on a 0.25/spl mu/m 2P3M CMOS technology are described. The test chips utilize a floating diffusion driving technique to achieve 3-transistors/pixel and 2-transistors/pixel respectively, and operate at 60 frames/s with 49mW dissipation.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"40 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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