2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)最新文献

筛选
英文 中文
A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump 一种带参考倍频器和补偿电荷泵的CMOS双带分数n合成器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332613
Hyungki Huh, Y. Koo, K. Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, D. Jeong, Wonchan Kim
{"title":"A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump","authors":"Hyungki Huh, Y. Koo, K. Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, D. Jeong, Wonchan Kim","doi":"10.1109/ISSCC.2004.1332613","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332613","url":null,"abstract":"A fully integrated dual-band frequency synthesizer in 0.35 /spl mu/m CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Cellular phones as embedded systems 作为嵌入式系统的蜂窝电话
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332581
Y. Neuvo
{"title":"Cellular phones as embedded systems","authors":"Y. Neuvo","doi":"10.1109/ISSCC.2004.1332581","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332581","url":null,"abstract":"The trend in handheld devices is toward smaller multifunctional terminals with continuously-improving end-user satisfaction. In addition to being difficult to fulfill separately, the different requirements are often contradictory. This statement applies especially well in the case of cellular phones. The speed of their development has been unequalled, while delivery volumes have grown all the time, being now over 400 million per annum. The high level of integration and other technical challenges make the cellular phone an ideal example of an embedded communications system with tough requirements. In this paper, technologies needed to assemble a cellular phone are studied from different angles. Overall power consumption is one of the key performance indicators. This translates to concern, both for power-amplifier and DSP efficiency in the talk mode, and for various leakage currents in analog and digital receiver circuits in the standby mode. The emerging multimedia capabilities call for better displays and enhanced audio performance. The increasing amount of software needed sets wholly new requirements for the processing power and memory size of the device. Third-generation cellular standards support high data rates, and are based on the most recent advances in the telecommunications sphere. Packet-switched traffic and Internet protocols are growing in importance, whereas other more-traditional radio interfaces are integrated into cellular phones to form multi-radio devices. Evidently, the power consumption is affected simultaneously. In this review paper, the cellular phone is analyzed as an embedded system from the integration, performance, and power-consumption angles. We discuss the following key issues concerning cellular phones: terminal trends and their impact on power economy; radio technologies and multiradio concepts; technological implementations; integration challenges; related solid-state-circuit research-and-development expectations.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 117
AC-only RF ID tags for barcode replacement 用于替换条形码的仅限交流射频ID标签
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332782
S. Briole, C. Pacha, K. Goser, A. Kaiser, R. Thewes, W. Weber, R. Brederlow
{"title":"AC-only RF ID tags for barcode replacement","authors":"S. Briole, C. Pacha, K. Goser, A. Kaiser, R. Thewes, W. Weber, R. Brederlow","doi":"10.1109/ISSCC.2004.1332782","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332782","url":null,"abstract":"An RF ID concept using ac-powered circuits without DC conversion is demonstrated for barcode replacement. A 32b codeword ID tag including an RF front-end, voltage limiter, frequency divider, ROM and power modulator has a 0.02mm/sup 2/ area in a 0.13/spl mu/m CMOS process. A packaging technology uses a sidewall contact to facilitate the assembly process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
4.3 GHz 44 /spl mu/W CMOS frequency divider 4.3 GHz 44 /spl mu/W CMOS分频器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332615
Ken Yamamoto, Minoru Fujishima
{"title":"4.3 GHz 44 /spl mu/W CMOS frequency divider","authors":"Ken Yamamoto, Minoru Fujishima","doi":"10.1109/ISSCC.2004.1332615","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332615","url":null,"abstract":"A microwatt frequency divider for the 2.5 GHz ISM band is proposed. The outputs are generated by pulse modulation of a ring oscillator. A power of 44 /spl mu/W at 4.3 GHz is achieved with a 0.2 /spl mu/m CMOS process. The core size is 10.8/spl times/10.5 /spl mu/m/sup 2/, and locking range is 2.3 GHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131223346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An 800 mW 10 Gb Ethernet transceiver in 0.13 /spl mu/m CMOS 一个800 mW的10 Gb以太网收发器,0.13 /spl mu/m CMOS
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332647
S. Sidiropoulos, N. Acharya, P. Chau, J. Dao, A. Feldman, H. Liaw, M. Loinaz, R. Narayanaswami, C. Portmann, S. Rabii, A. Salleh, S. Sheth, L. Thon, K. Vleugels, P. Yue, D. Stark
{"title":"An 800 mW 10 Gb Ethernet transceiver in 0.13 /spl mu/m CMOS","authors":"S. Sidiropoulos, N. Acharya, P. Chau, J. Dao, A. Feldman, H. Liaw, M. Loinaz, R. Narayanaswami, C. Portmann, S. Rabii, A. Salleh, S. Sheth, L. Thon, K. Vleugels, P. Yue, D. Stark","doi":"10.1109/ISSCC.2004.1332647","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332647","url":null,"abstract":"A fully integrated 10 Gb Ethernet transceiver IC using a standard 0.13 /spl mu/m CMOS process integrates 10.3 Gb/s and 4/spl times/3.12 Gb/s analog front-ends, with Layer-1 coding and management functionality. The 2.5/spl times/5 mm/sup 2/ IC exceeds both 10GE and SONET specifications, and dissipates 800 mW from its 1.2/2.5 V supplies.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An opamp with common-mode linearized input stage 具有共模线性化输入级的运放
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332796
N. Carter
{"title":"An opamp with common-mode linearized input stage","authors":"N. Carter","doi":"10.1109/ISSCC.2004.1332796","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332796","url":null,"abstract":"Wideband large-signal distortion has been optimized by applying a common-mode linearization technique to the amplifier input stage. An operational amplifier has been fabricated in a 6 GHz f/sub T/ dielectrically-isolated complementary bipolar process that achieves 1 nv//spl radic/Hz voltage noise, better than 90 dBc distortion for a 2 V/sub pp/ 10 MHz input signal, a 2 GHz GBW, and 500 /spl mu/V V/sub os/.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1GHz CMOS analog-front-end for a partial-response read channel 用于部分响应读通道的1GHz CMOS模拟前端
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332778
D. Sun, A. Xotta, A. Abidi
{"title":"A 1GHz CMOS analog-front-end for a partial-response read channel","authors":"D. Sun, A. Xotta, A. Abidi","doi":"10.1109/ISSCC.2004.1332778","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332778","url":null,"abstract":"An analog front-end including a continuous-time equalizer to shape the received waveform into a 6-sample target, and a DFE-driven timing recovery loop is presented. With soft Viterbi detection, sensitivity is within 1.5dB of simulations at a rate of 24/25 and user density of 3.4. The 0.35 /spl mu/m CMOS chip consumes 240mW at 800MHz, and 380mW at 1 GHz clock rates.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133726162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR 具有72 dB信噪比和86 dB SFDR的无镜像双路带通/spl Sigma//spl Delta/调制器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332605
F. Ying, F. Maloberti
{"title":"A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR","authors":"F. Ying, F. Maloberti","doi":"10.1109/ISSCC.2004.1332605","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332605","url":null,"abstract":"A cross-coupled two-path /spl Sigma//spl Delta/ architecture generates transmission zeros at 1/3 of the clock frequency, thereby achieving a mirror image free response. The chip uses 0.18 /spl mu/m CMOS technology and is clocked at 2/spl times/60 MHz with a 40 MHz IF. The modulator achieves an 86 dB SFDR with a 2.5 MHz bandwidth and consumes 150 mW from a 1.8 V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133983735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A resume-standby application processor for 3G cellular phones 一个用于3G移动电话的恢复待机应用程序处理器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332731
T. Kamei, M. Ishikawa, T. Hiraoka, T. Irita, M. Abe, Y. Saito, Y. Tawara, H. Ide, M. Furuyama, S. Tamaki, Y. Yasu, Y. Shimazaki, M. Yamaoka, H. Mizuno, N. Irie, O. Nishii, F. Arakawa, K. Hirose, S. Yoshioka, T. Hattori
{"title":"A resume-standby application processor for 3G cellular phones","authors":"T. Kamei, M. Ishikawa, T. Hiraoka, T. Irita, M. Abe, Y. Saito, Y. Tawara, H. Ide, M. Furuyama, S. Tamaki, Y. Yasu, Y. Shimazaki, M. Yamaoka, H. Mizuno, N. Irie, O. Nishii, F. Arakawa, K. Hirose, S. Yoshioka, T. Hattori","doi":"10.1109/ISSCC.2004.1332731","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332731","url":null,"abstract":"A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut off.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134329562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Designing outside rail constraints 钢轨外约束设计
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332630
A. Annema, Bram Nauta, R. V. Langevelde, Hans Tuinhout
{"title":"Designing outside rail constraints","authors":"A. Annema, Bram Nauta, R. V. Langevelde, Hans Tuinhout","doi":"10.1109/ISSCC.2004.1332630","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332630","url":null,"abstract":"CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115725273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信