用于部分响应读通道的1GHz CMOS模拟前端

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332778

D. Sun, A. Xotta, A. Abidi

{"title":"用于部分响应读通道的1GHz CMOS模拟前端","authors":"D. Sun, A. Xotta, A. Abidi","doi":"10.1109/ISSCC.2004.1332778","DOIUrl":null,"url":null,"abstract":"An analog front-end including a continuous-time equalizer to shape the received waveform into a 6-sample target, and a DFE-driven timing recovery loop is presented. With soft Viterbi detection, sensitivity is within 1.5dB of simulations at a rate of 24/25 and user density of 3.4. The 0.35 /spl mu/m CMOS chip consumes 240mW at 800MHz, and 380mW at 1 GHz clock rates.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 1GHz CMOS analog-front-end for a partial-response read channel\",\"authors\":\"D. Sun, A. Xotta, A. Abidi\",\"doi\":\"10.1109/ISSCC.2004.1332778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An analog front-end including a continuous-time equalizer to shape the received waveform into a 6-sample target, and a DFE-driven timing recovery loop is presented. With soft Viterbi detection, sensitivity is within 1.5dB of simulations at a rate of 24/25 and user density of 3.4. The 0.35 /spl mu/m CMOS chip consumes 240mW at 800MHz, and 380mW at 1 GHz clock rates.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"147 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

模拟前端包括一个连续时间均衡器，将接收到的波形塑造成一个6采样的目标，并提出了一个dfe驱动的定时恢复环路。使用软Viterbi检测，在24/25的速率和3.4的用户密度下，灵敏度在模拟的1.5dB以内。0.35 /spl mu/m的CMOS芯片在800MHz时功耗为240mW，在1ghz时功耗为380mW。

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A 1GHz CMOS analog-front-end for a partial-response read channel

An analog front-end including a continuous-time equalizer to shape the received waveform into a 6-sample target, and a DFE-driven timing recovery loop is presented. With soft Viterbi detection, sensitivity is within 1.5dB of simulations at a rate of 24/25 and user density of 3.4. The 0.35 /spl mu/m CMOS chip consumes 240mW at 800MHz, and 380mW at 1 GHz clock rates.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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