A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332605

F. Ying, F. Maloberti

引用次数: 19

Abstract

A cross-coupled two-path /spl Sigma//spl Delta/ architecture generates transmission zeros at 1/3 of the clock frequency, thereby achieving a mirror image free response. The chip uses 0.18 /spl mu/m CMOS technology and is clocked at 2/spl times/60 MHz with a 40 MHz IF. The modulator achieves an 86 dB SFDR with a 2.5 MHz bandwidth and consumes 150 mW from a 1.8 V supply.

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具有72 dB信噪比和86 dB SFDR的无镜像双路带通/spl Sigma//spl Delta/调制器

交叉耦合双路/spl Sigma//spl Delta/架构在时钟频率的1/3处产生传输零点，从而实现无镜像响应。该芯片采用0.18 /spl mu/m CMOS技术，时钟频率为2/spl times/60 MHz，中频为40 MHz。该调制器实现了86 dB的SFDR，带宽为2.5 MHz，从1.8 V电源消耗150 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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