一种带参考倍频器和补偿电荷泵的CMOS双带分数n合成器

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332613

Hyungki Huh, Y. Koo, K. Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, D. Jeong, Wonchan Kim

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引用次数: 48

摘要

采用0.35 /spl mu/m CMOS技术的全集成双带频率合成器在PCS频带的1.25 MHz偏移时，使用参考倍频器可实现-141 dBc/Hz的相位噪声。分数杂散减少了8.6分贝在50千赫偏移与复制补偿电荷泵。

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A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

A fully integrated dual-band frequency synthesizer in 0.35 /spl mu/m CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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