{"title":"90nm制程的可扩展X86 CPU设计","authors":"J. Schutz, C. Webb","doi":"10.1109/ISSCC.2004.1332594","DOIUrl":null,"url":null,"abstract":"A third generation Pentium/sup /spl reg//4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"A scalable X86 CPU design for 90 nm process\",\"authors\":\"J. Schutz, C. Webb\",\"doi\":\"10.1109/ISSCC.2004.1332594\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A third generation Pentium/sup /spl reg//4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332594\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332594","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A third generation Pentium/sup /spl reg//4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.