A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332692

S. Limotyrakis, S.D. Kulchycki, D. Su, B. Wooley

引用次数: 13

Abstract

This paper presents a 150 MS/s 8 bit time-interleaved ADC which has been built in 0.18 /spl mu/m CMOS. Segmentation of the track-and-hold into separate circuits, driving the 1st stage comparators and two interleaved residue paths, together with signal scaling, results in a 45.4 dB SNDR for an 80 MHz input frequency, while dissipating 71 mW from a 1.8 V supply.

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一个150MS/s 8b 71mW时间交错ADC在0.18/spl μ m CMOS

本文提出了一种基于0.18 /spl μ m CMOS芯片的150 MS/s 8位时间交错ADC。将跟踪保持分割成单独的电路，驱动第一级比较器和两个交错的残留路径，再加上信号缩放，在80 MHz输入频率下产生45.4 dB SNDR，同时从1.8 V电源消耗71 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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