2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)最新文献_第2页

Fast event-driven incremental learning of hand symbols 快速事件驱动的手部符号增量学习

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771472

Iulia-Alexandra Lungu, Shih-Chii Liu, T. Delbrück

{"title":"Fast event-driven incremental learning of hand symbols","authors":"Iulia-Alexandra Lungu, Shih-Chii Liu, T. Delbrück","doi":"10.1109/AICAS.2019.8771472","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771472","url":null,"abstract":"This paper describes a hand symbol recognition system that can quickly be trained to incrementally learn to recognize new symbols using about 100 times less data and time than by using conventional training. It is driven by frames from a Dynamic Vision Sensor (DVS) event camera. Conventional cameras have very redundant output, especially at high frame rates. Dynamic vision sensors output sparse and asynchronous brightness change events that occur when an object or the camera is moving. Images consisting of a fixed number of events from a DVS drive recognition and incremental learning of new hand symbols in the context of a RoShamBo (rock-paper-scissors) demonstration. Conventional training on the original RoShamBo dataset requires about 12.5h compute time on a desktop GPU using the 2.5 million images in the base dataset. Novel symbols that a user shows for a few tens of seconds to the system can be learned on-the-fly using the iCaRL incremental learning algorithm with 3 minutes of training time on a desktop GPU, while preserving recognition accuracy of previously trained symbols. Our system runs a residual network with 32 layers and maintains 88.4% after 100 epochs or 77% after 5 epochs overall accuracy after 4 incremental training stages. Each stage adds an additional 2 novel symbols to the base 4 symbols. The paper also reports an inexpensive robot hand used for live demonstrations of the base RoShamBo game.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116665480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Towards Workload-Balanced, Live Deep Learning Analytics for Confidentiality-Aware IoT Medical Platforms 面向具有保密性的物联网医疗平台的工作负载平衡、实时深度学习分析

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771558

Jose Granados, Haoming Chu, Z. Zou, Lirong Zheng

{"title":"Towards Workload-Balanced, Live Deep Learning Analytics for Confidentiality-Aware IoT Medical Platforms","authors":"Jose Granados, Haoming Chu, Z. Zou, Lirong Zheng","doi":"10.1109/AICAS.2019.8771558","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771558","url":null,"abstract":"Internet of Things (IoT) applications for healthcare are one of the most studied aspects in the research landscape due to the promise of more efficient resource allocation for hospitals and as a companion tool for health professionals. Yet, the requirements in terms of low power, latency and knowledge extraction from the large amount of physiological data generated represent a challenge to be addressed by the research community. In this work, we examine the balance between power consumption, performance and latency among edge, gateway, fog and cloud layers in an IoT medical platform featuring inference by Deep Learning models. We setup an IoT architecture to acquire and classify multichannel electrocardiogram (ECG) signals into normal or abnormal states which could represent a clinically relevant condition by combining custom embedded devices with contemporary open source machine learning packages such as TensorFlow. Different hardware platforms are tested in order to find the best compromise in terms of convenience, latency, power consumption and performance. Our experiments indicate that the real time requisites are fulfilled, however there is a need to reduce energy expenditure by means of incorporating low power SoCs with integrated neuromorphic blocks.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125608441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Accelerating CNN-RNN Based Machine Health Monitoring on FPGA FPGA加速基于CNN-RNN的机器健康监测

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771482

Xiaoyu Feng, Jinshan Yue, Qingwei Guo, Huazhong Yang, Yongpan Liu

引用次数: 1

Accelerator Design for Vector Quantized Convolutional Neural Network 矢量量化卷积神经网络加速器设计

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771469

Yi-Heng Wu, Heng Lee, Yu Sheng Lin, Shao-Yi Chien

{"title":"Accelerator Design for Vector Quantized Convolutional Neural Network","authors":"Yi-Heng Wu, Heng Lee, Yu Sheng Lin, Shao-Yi Chien","doi":"10.1109/AICAS.2019.8771469","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771469","url":null,"abstract":"In recent years, deep convolutional neural networks (CNNs) achieve ground-breaking success in many computer vision research fields. Due to the large model size and tremendous computation of CNNs, they cannot be efficiently executed in small devices like mobile phones. Although several hardware accelerator architectures have been developed, most of them can only efficient address one of the two major layers in CNN, convolutional (CONV) and fully connected (FC) layers. In this paper, based on algorithm-architecture-co-exploration, our architecture targets at executing both layers with high efficiency. Vector quantization technique is first selected to compress the parameters, reduce the computation, and unify the behaviors of both CONV and FC layers. To fully exploit the gain of vector quantization, we then propose an accelerator architecture for quantized CNN. Different DRAM access schemes are employed to reduce DRAM access. We also design a high-throughput processing element architecture to accelerate quantized layers. Compare to previous accelerators for CNN, the proposed architecture achieves 1.2–5x less DRAM access and 1.5–5x higher throughput for both CONV and FC layers.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

CNNP-v2:An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture CNNP-v2:一种以内存为中心的高能效卷积神经网络处理器架构

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771617

Sungpill Choi, Kyeongryeol Bong, Donghyeon Han, H. Yoo

引用次数: 6

Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing 用于神经网络处理的精度可扩展乘累积单元综述

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771610

Vincent Camus, C. Enz, M. Verhelst

{"title":"Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing","authors":"Vincent Camus, C. Enz, M. Verhelst","doi":"10.1109/AICAS.2019.8771610","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771610","url":null,"abstract":"The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way towards processing in mobile devices and IoT nodes. Precision-scalable MAC architectures optimized for neural networks have recently gained interest thanks to their subword parallel or bit-serial capabilities. Yet, it has been hard to make a fair judgment of their relative benefits as they have been implemented with different technologies and performance targets. In this work, run-time configurable MAC units from ISSCC 2017 and 2018 are implemented and compared objectively under diverse precision scenarios. All circuits are synthesized in a 28nm commercial CMOS process with precision ranging from 2 to 8 bits. This work analyzes the impact of scalability and compares the different MAC units in terms of energy, throughput and area, aiming to understand the optimal architectures to reduce computation costs in neural-network processing.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123478511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Flyintel – a Platform for Robot Navigation based on a Brain-Inspired Spiking Neural Network Flyintel——一个基于大脑激发脉冲神经网络的机器人导航平台

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771614

Huang-Yu Yao, Hsuan-Pei Huang, Yu-Chi Huang, C. Lo

引用次数: 2

Slasher: Stadium racer car for event camera end-to-end learning autonomous driving experiments Slasher:体育场赛车，用于事件相机端到端学习自动驾驶实验

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771520

Yuhuang Hu, Hong Ming Chen, T. Delbrück

引用次数: 2

Novel Sleep Apnea Detection Based on UWB Artificial Intelligence Mattress 基于超宽带人工智能床垫的新型睡眠呼吸暂停检测

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771598

Chiapin Wang, Jen-Hau Chan, Shih-Hau Fang, Ho-Ti Cheng, Yeh-Liang Hsu

引用次数: 5

Sparse Autoencoder with Attention Mechanism for Speech Emotion Recognition 基于注意机制的稀疏自编码器语音情绪识别

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2019-03-18 DOI: 10.1109/AICAS.2019.8771593

Ting-Wei Sun, A. Wu

引用次数: 11