1991, Proceedings. International Test Conference最新文献

{"title":"Logic Partitioning and Resynthesis for Testability","authors":"K. De, P. Banerjee","doi":"10.1109/TEST.1991.519757","DOIUrl":"https://doi.org/10.1109/TEST.1991.519757","url":null,"abstract":"","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CASE STUDY OF MIXED SIGNAL FAULT ISOLATION: KNOWLEDGE BASED VS. DECISION TREE PROGRAMMING","authors":"Charles W. Buenzli, Robert Gonzalez","doi":"10.1109/TEST.1991.519730","DOIUrl":"https://doi.org/10.1109/TEST.1991.519730","url":null,"abstract":"Comparison of current design and functional test practices for digital circuits versus analog circuits reveals a significant lag in the availability and sophistication of analog design tools, DFT techniques, design-to-test links, and diagnostic aides. Though hardware advances such as VXI and software advances such as the Standard Commands for Programmable Instruments (SCPI) reduce the time and expense of developing analog gobo go functional test programs, there has not been a similar advance in analog diagnostics. As a result, most electronic manufacturers and depots rely on skilled technicians to manually troubleshoot functional test failures. The scarcity and cost of skilled technicians and the increasing mix and complexity of analog (and mixed signal) circuits point to a strong need for automated analog diagnostics.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130466585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS","authors":"A. Meixner, Wojciech Maly","doi":"10.1109/TEST.1991.519719","DOIUrl":"https://doi.org/10.1109/TEST.1991.519719","url":null,"abstract":"The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128329264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A GENERIC METHOD TO DEVELOP A DEFECT MONITORING SYSTEM FOR IC PROCESSES","authors":"E. Bruls, F. Camerik, H. Kretschman, J. Jess","doi":"10.1109/TEST.1991.519513","DOIUrl":"https://doi.org/10.1109/TEST.1991.519513","url":null,"abstract":"Nowadays, the IC features are still becoming smaller, the areas larger and the packing densities higher. Thus, the occurrence of defects has a growing impact on production yields. Defect monitoring systems are widely used to obtain information about these defects. This paper describes a process-independent method to develop such a defect monitoring system. This implies that rules are given for the design of the monitor, the required resistance measurements, the applied data processing and the data presentation. This method can be applied to design monitors for various applications. For example, the monitor can contain one or more layers and can be process or product-related. An application of the method is also shown.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134185799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A FLEXIBLE APPROACH TO TEST PROGRAM CROSS COMPILERS","authors":"Michael A. Perugini","doi":"10.1109/TEST.1991.519777","DOIUrl":"https://doi.org/10.1109/TEST.1991.519777","url":null,"abstract":"The initial development costs of test programs and test hardvvare range from $5,000 to $30,000 or more. As device speeds or production needs increase, the need to test an existing device on a different tester often arises. A solution to minimize this development cost is to recycle the exixting test program, patterns and the device interface boards. This paper describes how the UNIX tools, LEX and YACC, were applied to solve this problem. In this case, Ando DIC 8035 test programs, paeterns and bad boards were used on a Credence Vista Series LT-1101 test system. The program ando2lt (Ando to LT) is the first of the test program crosscompilers using these tools. The flexibility of this approach led to the reuse of over 44% of the ando2lt code in the second cross-compiler sts2It.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131754041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EE CURRICULUM - CONTINUOUS PROCESS IMPROVEMENT?","authors":"C. Hawkins, Richard H. Williams","doi":"10.1109/TEST.1991.519792","DOIUrl":"https://doi.org/10.1109/TEST.1991.519792","url":null,"abstract":"Times are changing. Products are more sophisticated; consumers expect higher quality, lower costs, and negligible hazards for people and environment; and competition dictates an ever reduced time between a product's concept and actual production. These changes demand that engineering education be re-evaluated. What are the relations between manufacturing and engineering education? Engineering education must put all components of manufacturing into context. It is not adversarial with the research and development component. Rather, we take the attitude of \"concurrent engineering\" [2] in placing R&D as a key member of a team with engineering design, manufacturing design, and the other disciplines.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AN APPROACH TO CHIP-INTERNAL CURRENT MONITORING AND MEASUREMENT USING AN ELECTRON BEAM TESTER","authors":"K. Helmreich, P. Nagel, W. Wolz, K. Müller-Glaser","doi":"10.1109/TEST.1991.519517","DOIUrl":"https://doi.org/10.1109/TEST.1991.519517","url":null,"abstract":"An innovative measurement and imaging technique for electron beam testers is introduced, that promises to expand the present applicability of such systems for chip-internal voltage measurements by the capability of chip-internal current measurement. The theoretical principles of the method are discussed and the effect is calculated analytically for a model arrangement. For more realistic measurement situations, the results of numerical calculations, showing the strength of the effect and its dependency of situational parameters, are presented. First experimental results are added. 1 MOTIVATION During the last years, the market share of mixed-signal designs could be observed to be continously increasing. This tendency led to the introduction of dedicated mixedsignal test systems. For prototype debugging of purely digital circuits, internal measurement tools like electron beam !esters (EBTs) have proved to be valuable and at the moment efforts are undertaken to enhance these tools also for application to mixed-signal circuils. The main task herewith is to improve the voltage resolution of the EBT by reducing system-inherent noise. Thus the measurement of analog voltage signals becomes available at an acceptable signal-to-noise ratio [Gar 871. However, information in analog circuitry is often carried by currents and therefore not accessible for measurement with an electron beam tester. On the other hand, the capability of measuring supply currents to chip internal function blocks would allow for some kind of chipinternal IDDQ technique also in digital circuits [Haw 891. But the task of current measurement on chip-internal wires has been ncglected so far. To date, no mechanism has been presented that allows contactless rno:iitoring and measurement of chip-internal currents using an electron beam technique. Neither the measuremenl of the voltage drop caused by the rcsistance of chip-internal wires nor the evaluation of the deflection of the primary beam due to the magnetic field around a current carrying wire (in the range of some pm/A) provides a practical access to chip-internal currents [He1 911. The following paper will describe a promising approach to such a technique, that exploits the interaction between the magnetic field around a current carrying wire and secondary electrons emitted from its surface. 2 PRINCIPLES The basic interaction between a current and a moving electron (e.g. secondary electron) is established by the magnetic field caused by this current. Therefore, the interaction process is described by Ampere's Law and the Lorentz force, aA at p = -e--eeV@+evx(ZZxAJ","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128976597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quality in test education?","authors":"K. Rose","doi":"10.1109/TEST.1991.519795","DOIUrl":"https://doi.org/10.1109/TEST.1991.519795","url":null,"abstract":"The short answer to the first question is that test engineers had better be seen by their managements as part of the solution rather than part of the problem. The long answer is that the drive to raise quality and lower cost in less time has definite implications for test engineering practice. Kaoru Ishikawa at the University of Tokyo has been a leader in adapting quality improvement techniques to the work place. He has suggested that quality management has evolved from final inspection to manufacturing control to design improvement Final inspection, testing, to determine whether a product should be selected or rejected does not, by itself, improve quality. However, a high reject rate does indicate poor quality and higher cost.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128533957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect Level Estimation of Random and Pseudorandom Testing","authors":"W. Jone","doi":"10.1109/TEST.1991.519736","DOIUrl":"https://doi.org/10.1109/TEST.1991.519736","url":null,"abstract":"In this work, sequential statistical analysis has been applied to determine the defect level of random and pseudorandom testing. Results derived using worst case analysis show that the defect level of pseudorandom testing is always no larger than the defect level of random testing. We also find that the defect level of random testing is a good approximation to that of pseudorandom testing, only if either the yield or circuit detectability is high.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Organized Firmware Verification Environment for the Programmable Image DSP","authors":"Y. Tashiro, H. Yamauchi, T. Minami, T. Tajiri, Yutaka Suzuki","doi":"10.1109/TEST.1991.519771","DOIUrl":"https://doi.org/10.1109/TEST.1991.519771","url":null,"abstract":"Our newly designed IDSP (Image Digita.1 Signal Processor)[1] requires a high throughput of at. least 300 NIOPS for real-time video signal processing systems (especially, for one-hoard CCITT standard p x 64 kb/s video codec ones) to enable both the parallel processing of plural pixel blocks and development in short TAT (turn-around-time). Moreover, t#he IDSP on the application systems requires soft,ware. IDSP testing, therefore, should be considered firmware testing, involving hardware and software verification. Iinpleinenting firmware test.ing, liowever, is a difficult task due to the necessity of verifying the real-time and parallel processing performance of’ the IDSP. The houiida.ry-scan tecliniciue devised by JTAG (Joint Test Action Group) is one attempt to debug a system wit11 multiprocessors.[’] 111 tliis t,echnique, a test bus controller assigns sciln paths on the system board that connects all processors’ and other devices’ scan paths and inputs and rea.ds serial data into a,nd from the a.ssigned scan path registers. However, scan path test pa,tterns, i.e., serial dat,a, have t.o he generakd for system testing. Generat,program-bus 1 programI sad-bus","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"49 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}