Low overhead built-in testable error detection and correction with excellent fault coverage

M. Katoozi, Arnold Nordsiek
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引用次数: 1

Abstract

A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.
低开销内置可测试的错误检测和纠正,具有良好的故障覆盖率
提出了一种内置可测试(BIT)错误检测与校正(EDAC)电路的设计方法,将测试硬件减少50%以上。用该技术设计和制造的lp CMOS, 16位EDAC在25 MHz的10p下具有>99%的故障覆盖率。无论EDAC的大小,内置测试仅通过一个门延迟影响速度性能。将各种故障注入芯片,验证内置测试的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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