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Built-in generation of functional broadside tests considering primary input constraints 考虑主要输入约束的内置功能侧测试生成
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591560
Bo Yao, I. Pomeranz, S. Venkataraman, M. E. Amyeen
{"title":"Built-in generation of functional broadside tests considering primary input constraints","authors":"Bo Yao, I. Pomeranz, S. Venkataraman, M. E. Amyeen","doi":"10.1145/2591513.2591560","DOIUrl":"https://doi.org/10.1145/2591513.2591560","url":null,"abstract":"This paper describes a method for built-in generation of functional broadside tests for a circuit that is embedded in a larger design, taking functional constraints on its primary input sequences into account. The constraints are captured by functional input sequences of the design. Specifically, the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MB-FICA: multi-bit fault injection and coverage analysis MB-FICA:多比特故障注入和覆盖分析
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591538
Chengxiang Jiang, Mojing Liu, B. Meyer
{"title":"MB-FICA: multi-bit fault injection and coverage analysis","authors":"Chengxiang Jiang, Mojing Liu, B. Meyer","doi":"10.1145/2591513.2591538","DOIUrl":"https://doi.org/10.1145/2591513.2591538","url":null,"abstract":"Recent studies have shown a dramatic increase in multi-bit upset (MBU) events and related errors as transistors continue to shrink.\u0000 To assist designers with addressing MBU in microprocessor register files, we have extended an architectural description language, ADL, to simulate and analyze the effect of MBU on the fault coverage of hardware mitigation techniques.\u0000 Our approach (a) considers the effect of SRAM layout on MBU patterns, (b) considers the data-dependent nature of transient upsets, and (c) runs benchmarks to completion to accurately evaluate coverage.\u0000 To accelerate fault injection campaigns, we propose a suite of techniques that reduce the execution time of individual trials without compromising accuracy by only simulating mitigation techniques when faults are present and stopping simulation entirely when all errors have been detected or corrected.\u0000 When evaluating parity, SECDED, and 2-bit 2D ECC, we achieve a mean fault injection performance speedup of 5.1x, but up to nearly 60x in one case.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract] 带时间裕度的后硅偏斜调谐PDE整定和定时试验调度[扩展摘要]
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591571
M. Kaneko
{"title":"Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]","authors":"M. Kaneko","doi":"10.1145/2591513.2591571","DOIUrl":"https://doi.org/10.1145/2591513.2591571","url":null,"abstract":"Post-Silicon clock-Skew Tuning (PSST) is a promising technology for improving performance-yield of VLSIs under process variations. On the other hand, the resultant circuit after PSST should be also robust for run-time timing variations due to the change of temperature, power supply noise, etc. So, post-silicon skew tuning problem considering timing margin arises. In this work, the timing margin in the context of PSST is defined in terms of control values for programmable delay elements (PDEs), and a novel PDE tuning algorithm considering timing margin is proposed. The key component of our PDE tuning procedure is a timing test considering timing margin, in which we need to use a set of different PDE settings (mu-margin PDE test-settings) from a designed (target) PDE setting. Discussions done in this work are devoted to reducing test cost in terms of the number of timing test as well as PDE setting cost in terms of the number of mu-margin PDE test-settings.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails 功率轨数有限的超动态电压缩放功率开关优化设计方法
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591585
Yanzhi Wang, X. Lin, Massoud Pedram
{"title":"Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails","authors":"Yanzhi Wang, X. Lin, Massoud Pedram","doi":"10.1145/2591513.2591585","DOIUrl":"https://doi.org/10.1145/2591513.2591585","url":null,"abstract":"Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation. Digital circuits supporting such burst-mode applications should work in both the near-threshold regime and the super-threshold regime for brief time periods. This work proposes the structure support of fine-grained ultra dynamic voltage scaling (UDVS) from the traditional strong-inversion region to the near-threshold region, with limitations on the number of power rails. The number, type, and size of the power switches are jointly optimized to minimize the overall energy consumption of the UDVS circuit block, meanwhile satisfying the target delay or frequency requirement at each DVS level. The proposed optimization framework properly accounts for the dynamic energy consumption as well as the leakage energy consumption through all the power switches during both the operation time and stand-by time of the circuit block. Experimental results on 22nm Predictive Technology Model demonstrate the effectiveness of the proposed optimization framework.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125992770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Level shifter planning for timing constrained multi-voltage SoC floorplanning 时序约束多电压SoC平面规划的电平移位器规划
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591587
Zhufei Chu, Yinshui Xia, Lunyao Wang
{"title":"Level shifter planning for timing constrained multi-voltage SoC floorplanning","authors":"Zhufei Chu, Yinshui Xia, Lunyao Wang","doi":"10.1145/2591513.2591587","DOIUrl":"https://doi.org/10.1145/2591513.2591587","url":null,"abstract":"To implement multi-voltage technique in SoC designs, level shifters (LSs) are essential modules which translate signals among different voltage domains. However, inserting LSs requires non-negligible area and timing overhead. In this paper, we study LS planning (LSP) method for timing constrained multi-voltage SoC floorplanning problem. The design flow consists of two phases. In phase I, to reserve the desired white space for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. In phase II, the main floorplanning loop is implemented. Different from previous works which do voltage assignment without physical information feedback, we build an inner loop between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 15% with 4% area increase.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123504159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM 3D-SWIFT:高性能3d堆叠宽IO DRAM
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591529
Zhang Tao, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie
{"title":"3D-SWIFT: a high-performance 3D-stacked wide IO DRAM","authors":"Zhang Tao, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie","doi":"10.1145/2591513.2591529","DOIUrl":"https://doi.org/10.1145/2591513.2591529","url":null,"abstract":"Wide IO has been standardized as a low-power, high-bandwidth DRAM for embedded system. The performance of Wide IO, however, is limited by the power constraint and unexploited fine-grained memory parallelism. In this work, we propose a novel architecture, 3D-SWIFT, that achieves high access parallelism by partitioning a memory bank into sub-banks with a fine access granularity, which takes advantage of 3D die-stacking. The power constraint is naturally eliminated by the fine-grained structure due to the reduced activation power. Moreover, we propose sub-bank autonomy and introduce corresponding management policies to enable an intelligent interface protocol. Thanks to sub-rank autonomy, the overhead of tracking huge concurrent accesses in the memory controller is significantly reduced, making our 3D-SWIFT architecture scalable for future memory systems. We evaluate our 3D-SWIFT and the results show that 3D-SWIFT can achieve 87.6% performance improvement compared to the state-of-the-art Wide IO.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control 使用自适应独立栅极控制在多种电压下工作的FinFET标准单元的能量优化尺寸
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591555
Yue Fu, Yanzhi Wang, X. Lin, Shahin Nazarian, Massoud Pedram
{"title":"Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control","authors":"Yue Fu, Yanzhi Wang, X. Lin, Shahin Nazarian, Massoud Pedram","doi":"10.1145/2591513.2591555","DOIUrl":"https://doi.org/10.1145/2591513.2591555","url":null,"abstract":"FinFET has been proposed as an alternative for bulk CMOS in the ultra-low power designs due to its more effective channel control, reduced random dopant fluctuation, higher ON/OFF current ratio, lower energy consumption, etc. The characteristics of FinFETs operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper introduces an analytical transregional FinFET model with high accuracy in both subthrehold and near-threshold regions. The unique feature of independent gate controls for FinFET devices is exploited for achieving a tradeoff between energy consumption and delay, and balancing the rise and fall times of FinFET gates. This paper proposes an effective design framework of FinFET standard cells based on the adaptive independent gate control method such that they can operate properly at all of subthreshold, near-threshold and super-threshold regions. The optimal voltage for independent gate control is derived so as to achieve equal rise and fall times or minimal energy-delay product at any supply voltage level.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121977350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An automated design approach to map applications on CGRAs 一种基于CGRAs的地图应用程序的自动化设计方法
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591552
T. Peyret, G. Corre, M. Thévenin, Kevin J. M. Martin, P. Coussy
{"title":"An automated design approach to map applications on CGRAs","authors":"T. Peyret, G. Corre, M. Thévenin, Kevin J. M. Martin, P. Coussy","doi":"10.1145/2591513.2591552","DOIUrl":"https://doi.org/10.1145/2591513.2591552","url":null,"abstract":"Coarse-Grained Reconfigurable Architectures (CGRAs) are promising high-performance and power-efficient platforms. However, their uses are still limited by the capability of mapping tools. This abstract paper outlines a new automated design flow to map applications on CGRAs. The interest of our method is shown through comparison with state of the art approaches.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Adaptive compressive sensing for low power wireless sensors 低功耗无线传感器的自适应压缩感知
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591537
Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, S. Tragoudas
{"title":"Adaptive compressive sensing for low power wireless sensors","authors":"Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, S. Tragoudas","doi":"10.1145/2591513.2591537","DOIUrl":"https://doi.org/10.1145/2591513.2591537","url":null,"abstract":"Compressive sensing has been demonstrated as an appealing technique in the implementation of low-power sensors. This work studies the feasibility and potential power savings by adaptively adjusting the sampling rates in compressive sensing operations, which is referred to as adaptive compressive sensing in this paper. The results reveal that the sparsity of many biomedical sensor signals varies over time and hence it is possible to perform such adaptive operations. The study also shows that the adaptive operation can lead to significant reduction on sensor node power consumption","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129200684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Highly adaptive and congestion-aware routing for 3D NoCs 用于3D noc的高度自适应和拥塞感知路由
ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591581
Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, S. Ko, Mark Zwolinski
{"title":"Highly adaptive and congestion-aware routing for 3D NoCs","authors":"Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, S. Ko, Mark Zwolinski","doi":"10.1145/2591513.2591581","DOIUrl":"https://doi.org/10.1145/2591513.2591581","url":null,"abstract":"In this paper, we propose a novel highly adaptive and congestion aware routing algorithm 3D meshes which is equally applicable to 2D meshes as well. The proposed algorithm allows cyclic dependencies in channel dependency graph (CDG) providing higher degree of adaptiveness. The algorithm uses congestion-aware channel selection strategy that results balanced distribution of traffic flows across the network. A packet follows non-minimal paths only when minimal paths are congested at the neighboring channels. The deadlock avoidance methodology adopted by our algorithm remains cost-efficient as it uses one extra virtual channel along each of Y and Z dimensions to achieve deadlock freedom.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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