ACM Great Lakes Symposium on VLSI最新文献_第5页

OCV-aware top-level clock tree optimization ocv感知的顶级时钟树优化

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591541

T. Chan, Kwangsoo Han, A. Kahng, Jae-Gon Lee, S. Nath

引用次数: 15

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures 基于网络自定义的内存映射方法设计无冲突并行硬件体系结构

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591532

Saeed Ur Reehman, C. Chavet, P. Coussy

{"title":"A memory mapping approach based on network customization to design conflict-free parallel hardware architectures","authors":"Saeed Ur Reehman, C. Chavet, P. Coussy","doi":"10.1145/2591513.2591532","DOIUrl":"https://doi.org/10.1145/2591513.2591532","url":null,"abstract":"Parallel hardware architectures are needed to achieve high throughput systems. Unfortunately, efficient parallel architectures often require removing memory access conflicts. This is particularly true when designing turbo-codes, channel interleaver or LDPC (Low Density Parity Check) codes architectures which are one of the most critical parts of parallel decoders. Many solutions are proposed in state of the art to find conflict free memory mapping but they are either limited to a subset of constraints, or result in high architectural cost. These drawbacks come from the interleaving law and the incompatibility between this law and the targeted interconnection network (in the coder/encoder architecture). In this paper we propose a conflict free memory mapping approach that is able to generate optimized hardware architectures by limiting these drawbacks. The proposed solution constructs a customized interconnection network by analyzing data access patterns defined in the interleaving law. Our approach is then compared to state of the art methods and its interest is shown through the design of parallel interleavers for HSPA.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems 采用自适应读电压阈值提高MLC NAND闪存系统的可靠性

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591594

N. Papandreou, Thomas Parnell, H. Pozidis, T. Mittelholzer, E. Eleftheriou, C. Camp, T. Griffin, G. Tressler, Andrew Walls

引用次数: 36

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories 亚16nm基于finet的STT-MRAM存储器中时间零变异性的建模和缓解

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591573

Matthias Hartmann, H. Kukner, Prashant Agrawal, P. Raghavan, L. Perre, W. Dehaene

引用次数: 0

Securely outsourcing power grid simulation on cloud 安全地将电网仿真外包到云端

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591547

Naval Gupte, Jia Wang

引用次数: 0

Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas 具有对数周期片上天线的高能效无线网络片上架构

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591566

Md Shahriar Shamim, N. Mansoor, A. Samaiyar, A. Ganguly, Sujay Deb, S. S. Ram

引用次数: 22

A novel low-power and in-place split-radix FFT processor 一种新颖的低功耗就地分基FFT处理器

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591563

Z. Qian, M. Margala

引用次数: 9

Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory 嵌入式动态随机存取存储器中鲁棒宽工作域低功耗电平移位器的设计与分析

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591533

Kenneth Ramclam, Swaroop Ghosh

引用次数: 1

EDA for extreme scale systems: design abstractions, metrics, and benchmarks 用于极端规模系统的EDA:设计抽象、度量和基准

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2597170

A. Jones

{"title":"EDA for extreme scale systems: design abstractions, metrics, and benchmarks","authors":"A. Jones","doi":"10.1145/2591513.2597170","DOIUrl":"https://doi.org/10.1145/2591513.2597170","url":null,"abstract":"The context for EDA research is rapidly changing thanks to enhanced and novel switching devices, manufacturing technologies, new application targets, and the increasing soft- ware development effort required for new ICs. These trends continue to expand the gap between the capabilities of systems and what can be utilized by designers. To address these problems requires a collaborative effort with indus- try researchers, academics, and funding agencies working together in close partnership. This talk describes recommendations from the recent CCC workshop series on EDA in the Extreme Scale era for improving the collaboration between IC designers and EDA. There remains a continued importance of effective design abstractions that facilitate research on EDA advances that can be effectively translated to actual design flows for relevant technologies. Further, these abstractions must be accompanied by (i) effective design metrics, especially for new technologies where optimization objectives may not be obvious, and (ii) appropriate benchmarks, especially for more established technologies where alternative optimization techniques must be carefully compared. Focus on these research directions for EDA will have direct impact to reduce the existing capabilities gap between tools and designers.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 一个完整的电子网络接口架构，用于新兴的光网络芯片上的全球无争用通信

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591536

Marta Ortín-Obón, L. Ramini, H. Tatenguem, V. Viñals, D. Bertozzi

引用次数: 7