ACM Great Lakes Symposium on VLSI最新文献_第6页

A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers 一种新的片上系统移动收发器基带滤波器混合信号自校正技术

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591522

Yongsuk Choi, Yong-Bin Kim

引用次数: 0

H.264 8x8 inverse transform architecture optimization H.264 8x8逆变换架构优化

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591564

F. Pereira, A. Soares, A. Susin, A. Bonatto, M. Negreiros

引用次数: 2

A generic implementation of a quantified predictor on FPGAs 量化预测器在fpga上的通用实现

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591517

G. Thomas, A. Elhossini, B. Juurlink

引用次数: 2

WeDBless: weighted deflection bufferless router for mesh NoCs WeDBless:用于网状noc的加权偏转无缓冲路由器

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591559

Simi Zerine Sleeba, John Jose, M. G. Mini

引用次数: 5

System-level reliability exploration framework for heterogeneous MPSoC 异构MPSoC系统级可靠性探索框架

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591519

Z. Wang, Chao Chen, Piyush Sharma, A. Chattopadhyay

引用次数: 5

New 4T-based DRAM cell designs 新的基于4t的DRAM单元设计

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591515

Wei Wei, K. Namba, F. Lombardi

引用次数: 1

VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract 提高通信性能的线性MIMO检测的VLSI实现:扩展摘要

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591551

Dominik Auras, D. Rieth, R. Leupers, G. Ascheid

引用次数: 2

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis 使用延迟不敏感的最大项合成来加固QDI电路以防止瞬态故障

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591531

Matheus T. Moreira, R. Guazzelli, G. Heck, Ney Laert Vilar Calazans

{"title":"Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis","authors":"Matheus T. Moreira, R. Guazzelli, G. Heck, Ney Laert Vilar Calazans","doi":"10.1145/2591513.2591531","DOIUrl":"https://doi.org/10.1145/2591513.2591531","url":null,"abstract":"The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the presence and propagation of transient faults. If these faults are latched, they will corrupt data validity and can make the whole circuit to stall, given the strict event ordering constraints imposed by handshaking protocols. This is particularly concerning for the delay-insensitive minterm synthesis logic style, widely adopted by asynchronous designers to implement combinatory quasi-delay-insensitive logic, because it makes extensive use of C-elements and these components are rather vulnerable to transient effects. This paper demonstrates that this logic style submits C-elements to their most vulnerable states during operation. It accordingly proposes the alternative use of the delay-insensitive maxterm synthesis for hardening QDI circuits against transient faults. The latter is a logic style based on the return-to-one 4-phase protocol. Although this style also relies on extensive usage of C-elements, the states where these components are most vulnerable are avoided. Results display improvements of over 300% in C-elements tolerance to transient faults, in the best case.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128538889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Reliability-aware cross-point resistive memory design 可靠性感知交叉点电阻式存储器设计

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591528

Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie

{"title":"Reliability-aware cross-point resistive memory design","authors":"Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie","doi":"10.1145/2591513.2591528","DOIUrl":"https://doi.org/10.1145/2591513.2591528","url":null,"abstract":"The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been developed and demonstrate attractive characteristics, such as fast read/write speed, low power consumption, high integrated density, and good scalability. Among them, the most attractive characteristic of ReRAM is its cross-point structure which features a 4F2 cell size. However, the existence of sneak current and voltage drop along the wire resistance in a cross-point array brings in extra design challenges. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this paper, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure modes on the reliability of cross-point array. We also propose an error resilient architecture which avoids unnecessary writes in the hard error detection unit. Experimental results show that our design can extend the lifetime of ReRAM up to 75% over the design without hard error detections and up to 12% over the design with \"write-verify\" detection mechanism.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130120476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Thermal-aware phase-based tuning of embedded systems 嵌入式系统的热感知相位调优

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591586

Tosiron Adegbija, A. Gordon-Ross

引用次数: 3