ACM Great Lakes Symposium on VLSI最新文献_第10页

RAPA: reliability-aware priority arbitration strategy for network on chip 基于片上网络的可靠性感知优先级仲裁策略

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206807

Jiajia Jiao, Yuzhuo Fu

{"title":"RAPA: reliability-aware priority arbitration strategy for network on chip","authors":"Jiajia Jiao, Yuzhuo Fu","doi":"10.1145/2206781.2206807","DOIUrl":"https://doi.org/10.1145/2206781.2206807","url":null,"abstract":"Reliability issue, especially from transient errors due to scaling IC technology, low voltage supply, high frequency and heavy thermal effects, particles emission etc, has become a challenge for NoC design. Focus on this problem, an effective Reliability-Aware Arbitration Strategy simplified as RAPA, is proposed in this paper to decide which flits should be prioritized in the network transmission for higher application-level reliability. Different from pervious performance-oriented arbitration strategies, it includes the application-level reliability requirement to determine the reliability priority ranking. Flits patching mechanism is also used for avoiding starvation. The evaluation metric is redefined to emphasizing application-level reliability. Finally, we verify the reliability based prioritization policy on cycle accurate platform. And the simulation results show that the averaged successful delivery rate is upgraded from three nine of round robin (RR), old age based arbitration(OA) to five nine of our method RAPA. Especially, 67.15%, 41.83% reliability improvement in rest unreliable space on average are obtained over typical RR policy and OA based arbitration policy respectively with guaranteed performance.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114095763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit 纳米级CMOS电路中自适应体偏置降低漏功率的方案

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206811

Jing Yang, Yong-Bin Kim

引用次数: 6

A denial-of-service resilient wireless NoC architecture 一种拒绝服务弹性无线NoC架构

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206844

A. Ganguly, M. Y. Ahmed, Anuroop Vidapalapati

引用次数: 17

Sustainable multi-core architecture with on-chip wireless links 具有片上无线链路的可持续多核架构

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206845

Jacob Murray, John Klingner, P. Pande, B. Shirazi

引用次数: 5

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage 三维fpga中的多路开关盒结构，以减少硅面积和提高TSV使用率

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206855

Marzieh Morshedzadeh, A. Jahanian

引用次数: 2

Extending symmetric variable-pair transitivities using state-space transformations 使用状态空间转换扩展对称变量对传递性

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206859

P. Maurer

引用次数: 1

A zero-overhead IC identification technique using clock sweeping and path delay analysis 零开销集成电路识别技术使用时钟扫描和路径延迟分析

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206806

Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor

引用次数: 11

Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs 基于SRAM和RRAM的3D mpsoc热管理策略的设计时性能评估

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206824

D. Brenner, Cory E. Merkel, D. Kudithipudi

{"title":"Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs","authors":"D. Brenner, Cory E. Merkel, D. Kudithipudi","doi":"10.1145/2206781.2206824","DOIUrl":"https://doi.org/10.1145/2206781.2206824","url":null,"abstract":"3D-ICs hold significant promise for future generation multi processor systems-on-chip due to their potential for increased performance, decreased power, heterogeneous integration, and reduced cost over planar ICs. However, the vertical integration of these structures exacerbates the heat dissipation and run-time thermal management issues. There have been a number of design- and run-time thermal management policies proposed, but few focus on examining overall system performance. Additionally, the heterogeneity of 3D-ICs allows for the integration of novel technologies, such as resistive random access memories (RRAMs), which offer higher density and lower power than traditional CMOS memory technologies. Our work presents a flexible design-time simulation framework to evaluate system performance and thermal profiles of 3D MPSoCs. We utilize this framework to study the effect of three dynamic thermal management policies (air-cooled load balancing, liquid-cooled load balancing, and air-cooled DVFS) on system performance and die temperature for multi-tiered 3D MPSoCs utilizing SRAM and RRAM-based L2 caches. We find that RRAM-based caches lower overall average maximum temperatures by 120 K and 24 K for air and liquid cooling systems, respectively (when compared to SRAM-based caches), at a worst-case performance delay of 47% and best-case delay of 13% for the parallel shared-memory benchmarks studied.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Alleviating NBTI-induced failure in off-chip output drivers 缓解nbti引起的片外输出驱动器故障

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206853

Bhavitavya Bhadviya, Ayan Mandal, S. Khatri

引用次数: 0

A scalable threshold logic synthesis method using ZBDDs 一种基于zbdd的可扩展阈值逻辑合成方法

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206856

Ashok Kumar Palaniswamy, S. Tragoudas

引用次数: 5