A zero-overhead IC identification technique using clock sweeping and path delay analysis

Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor
{"title":"A zero-overhead IC identification technique using clock sweeping and path delay analysis","authors":"Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor","doi":"10.1145/2206781.2206806","DOIUrl":null,"url":null,"abstract":"The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2206781.2206806","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.
零开销集成电路识别技术使用时钟扫描和路径延迟分析
集成电路(ic)的假冒已成为电子工业的一个主要问题。假冒ic进入关键应用程序的供应链可能会对这些系统的安全性和可靠性产生重大影响。本文提出了一种通过路径延迟分析来唯一识别集成电路的新方法。该方法在面积、时间或功耗方面没有开销,因为它提取了IC的固有路径延迟变化信息。90nm技术的仿真结果和90nm fpga的实验结果证明了我们技术的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信