{"title":"Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit","authors":"Jing Yang, Yong-Bin Kim","doi":"10.1145/2206781.2206811","DOIUrl":null,"url":null,"abstract":"This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2206781.2206811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.