Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory

Level shifters (LS) are crucial components in low power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. Another important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We explore one such application in embedded Dynamic Random Access Memories (eDRAM) where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of eDRAM. Furthermore the delay of LS under worse case process corners can cause functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS can improve the worst case speed from 2.7%-43%. We also propose power-gating for LSs to improve the retention time and bandwidth with minimal power and area overhead.