MB-FICA: multi-bit fault injection and coverage analysis

Abstract

Recent studies have shown a dramatic increase in multi-bit upset (MBU) events and related errors as transistors continue to shrink. To assist designers with addressing MBU in microprocessor register files, we have extended an architectural description language, ADL, to simulate and analyze the effect of MBU on the fault coverage of hardware mitigation techniques. Our approach (a) considers the effect of SRAM layout on MBU patterns, (b) considers the data-dependent nature of transient upsets, and (c) runs benchmarks to completion to accurately evaluate coverage. To accelerate fault injection campaigns, we propose a suite of techniques that reduce the execution time of individual trials without compromising accuracy by only simulating mitigation techniques when faults are present and stopping simulation entirely when all errors have been detected or corrected. When evaluating parity, SECDED, and 2-bit 2D ECC, we achieve a mean fault injection performance speedup of 5.1x, but up to nearly 60x in one case.