ACM Great Lakes Symposium on VLSI最新文献_第3页

Efficient parallel beamforming for 3D ultrasound imaging 高效平行波束形成的三维超声成像

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591599

Pirmin Vogel, Andrea Bartolini, L. Benini

引用次数: 14

A semi-formal approach for analog circuits behavioral properties verification 模拟电路行为特性验证的半形式化方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591578

Ons Lahiouel, Henda Aridhi, M. Zaki, S. Tahar

引用次数: 2

Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory 定制一个开源处理器，使其适合具有共享L1内存的超低功耗集群

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591569

Michael Gautschi, D. Rossi, L. Benini

引用次数: 25

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages 使用双电源电压的可配置结构化ASIC的逻辑模块和设计方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591601

Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin

引用次数: 0

A new DRAM architecture and its control method for the system power consumption 一种新的DRAM架构及其系统功耗控制方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591516

Y. Riho, K. Nakazato

{"title":"A new DRAM architecture and its control method for the system power consumption","authors":"Y. Riho, K. Nakazato","doi":"10.1145/2591513.2591516","DOIUrl":"https://doi.org/10.1145/2591513.2591516","url":null,"abstract":"Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a re-write operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. According to a new proposed method the refresh operation frequency and its power consumption reduce to 1/(2 to the Nth) (N=1, 2, 3, 4) when full memory capacity is not required, by effectively extending the refresh operation interval. The proposal includes the conversion from 1 cell/bit to (2 to the Nth) cells/bit, which reduces the variation of retention times among memory cells. This leads the refresh operation frequency from 1/(2 to the Nth) to 1/(2 to the Nth) X 1/(2 to the Nth), while it accompanies the additional charging power for the composed memory cell. A system can select the best way of 1 cell/bit and (2 to the Nth) cells/bit from the total viewpoint, while all conventional functions and operations in the full array access mode are fully compatible.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131262109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield 宏观故障:一种新的故障模型及其对容错和制造良率的影响

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591556

T. Lam, Xing Wei, W. Jone, Yi Diao, Yu-Liang Wu

{"title":"On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield","authors":"T. Lam, Xing Wei, W. Jone, Yi Diao, Yu-Liang Wu","doi":"10.1145/2591513.2591556","DOIUrl":"https://doi.org/10.1145/2591513.2591556","url":null,"abstract":"A macro-fault is defined as a group of signal faults such that the errors induced cannot be observed unless two or more faults (either permanent or temporary) in the group happen simultaneously. Since adding a redundant (alternative) wire for an existing (target) wire can mask some certain faults of these two wires mutually, a macro-fault can be formed by redundant wire addition. The faults that are dominated by or equivalent to the masked faults are also included in the macro-fault. As the feature size of integrated circuit technologies continue to scale down, manufacturing fault-free chips is getting more difficult and fault tolerance techniques will become more critical. In the past, redundancy has been adopted for memory for improving fault tolerance. For critical circuit components, even the costly triple modular redundancy techniques have to be applied. In this work, we study the implications of our new fault model, macro-fault, on the potential impact on fault tolerance and manufacturing yield. Based on the findings, a heuristic approach based on redundant wire addition is designed for improving fault tolerance. The approach can be incorporated with other fault tolerance techniques to form a hierarchical cross-layer fault tolerance scheme.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127747132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel parallel adaptation of an implicit path delay grading method 一种新的并行自适应隐式路径延迟分级方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591539

Joseph Lenox, S. Tragoudas

引用次数: 1

Modeling of the charging behavior of li-ion batteries based on manufacturer's data 基于制造商数据的锂离子电池充电行为建模

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591592

Alessandro Sassone, Donghwa Shin, Alberto Bocca, A. Macii, E. Macii, M. Poncino

引用次数: 5

Smart nodes of internet of things (IoT): a hardware perspective view & implementation 物联网智能节点:硬件视角与实现

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2597169

E. Sánchez-Sinencio

引用次数: 4

Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures FPGA中的硬件木马攻击:威胁分析及有效对策

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591520

Sanchita Mal-Sarkar, A. Krishna, A. Ghosh, S. Bhunia

{"title":"Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures","authors":"Sanchita Mal-Sarkar, A. Krishna, A. Ghosh, S. Bhunia","doi":"10.1145/2591513.2591520","DOIUrl":"https://doi.org/10.1145/2591513.2591520","url":null,"abstract":"Reconfigurable hardware including Field programmable gate arrays (FPGAs) are being used in a wide range of embedded applications including signal processing, multimedia, and security. FPGA device production is often outsourced to off-shore facilities for economic reasons. This opens up the opportunities for insertion of malicious design alterations in the foundry, referred to as hardware Trojan attacks, to cause logical and physical malfunction. The vulnerability of these devices to hardware attacks raises security concerns regarding hardware and design assurance. In this paper, we analyze hardware Trojan attacks in FPGA considering diverse activation and payload characteristics and derive a taxonomy of Trojan attacks in FPGA. To our knowledge, this is the first effort to analyze Trojan threats in FPGA hardware. Next, we propose a novel redundancy-based protection approach based on Trojan tolerance that modifies the application mapping process to provide high-level of protection against Trojans of varying forms and sizes. We show that the proposed approach incurs significantly higher security at lower overhead than conventional fault-tolerance schemes by exploiting the nature of Trojans and reconfiguration of FPGA resources.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129780511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44