Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin
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Logic block and design methodology for via-configurable structured ASIC using dual supply voltages
This paper presents a via-configurable logic block and a design methodology for realizing fine-grained dual-supply-voltage structured ASIC. Experiments with a 90nm process technology show that, given various timing budgets, our approach can achieve up to 44% energy reduction with 1.6% area overhead on level converters. Compared with GECVS, our approach converts up to 39% more high-supply voltage gates into low-supply voltage gates.
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