ACM Great Lakes Symposium on VLSI最新文献_第2页

A new methodology for reduced cost of resilience 一种降低弹性成本的新方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591600

A. Kahng, Seokhyeong Kang, Jiajia Li

{"title":"A new methodology for reduced cost of resilience","authors":"A. Kahng, Seokhyeong Kang, Jiajia Li","doi":"10.1145/2591513.2591600","DOIUrl":"https://doi.org/10.1145/2591513.2591600","url":null,"abstract":"Resilient design techniques are used to (i) ensure correct operation under dynamic variations; and (ii) improve design performance (e.g., through timing speculation). However, significant overheads (e.g., 17% and 15% energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For instance, resilient designs require additional circuits to detect and correct timing errors. Further, when there is an error, the additional cycles needed to restore a previous correct state degrade throughput, which diminishes the performance benefit of using resilient designs. In this work, we propose a methodology for resilient design implementation to minimize the costs of resilience in terms of power, area and throughput degradation. Our methodology uses two levers: selective-endpoint optimization (i.e., sensitivity-based margin insertion) and clock skew optimization. We integrate the two optimization techniques in an iterative optimization flow which comprehends toggle rate information and the tradeoff between cost of resilience and margin on combinational paths. Our proposed flow achieves energy reductions of up to 19% and 21% compared to a conventional design (with only margin used to attain robustness) and a brute-force implementation, respectively. These benefits increase in the context of an adaptive voltage scaling strategy.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125381922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A feasibility study on robust programmable delay element design based on neuron-MOS mechanism 基于神经元- mos机制的鲁棒可编程延迟元件设计可行性研究

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591591

Renyuan Zhang, M. Kaneko

引用次数: 2

Create, then innovate 先创造，再创新

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2597171

Gene A. Frantz

引用次数: 0

An area efficient low power high speed S-Box implementation using power-gated PLA 采用功率门控PLA的面积高效低功耗高速S-Box实现

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591575

Ho Joon Lee, Yong-Bin Kim

引用次数: 0

A qualitative simulation approach for verifying PLL locking property 一种验证锁相环锁定特性的定性仿真方法

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591593

Ibtissem Seghaier, Henda Aridhi, M. Zaki, S. Tahar

引用次数: 8

TSV power supply array electromigration lifetime analysis in 3D ICS 三维集成电路中TSV电源阵列电迁移寿命分析

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591567

Qiaosha Zou, Zhang Tao, Cong Xu, Yuan Xie

引用次数: 0

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness 一种基于tsv交叉链接的三维时钟网络合成方法，以提高鲁棒性

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591584

Rickard Ewetz, A. Udupa, G. Subbarayan, Cheng-Kok Koh

{"title":"A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness","authors":"Rickard Ewetz, A. Udupa, G. Subbarayan, Cheng-Kok Koh","doi":"10.1145/2591513.2591584","DOIUrl":"https://doi.org/10.1145/2591513.2591584","url":null,"abstract":"To obtain high yield for 3D ICs, random open defects, process variations, and thermal induced stress are key issues that must be addressed when synthesizing 3D clock networks. Current research on 3D clock synthesis often focuses on the construction and optimization of a 3D clock tree topology. Moreover, extra circuitry has been proposed to enable pre-bond testing and substitution of through silicon vias (TSVs) with random open defects. However, tree structures inherently have limited robustness to variations and may suffer failures arising from defects and/or process variations. To counter such problems, we propose to use TSVs to add redundancy in a 3D clock network. The proposed 3D network would have a complete 2D clock network on each die, facilitating pre-bond testing. Also, cross links would be inserted within each die using wires and across dies using TSVs to improve timing robustness within each die and across dies, respectively. Moreover, clock buffers are placed outside of zones that have high TSV-induced stress that could influence carrier mobility. Experimental results show that the proposed 3D clock networks have no failures due to random open defects, and on the average have 53% lower skew compared to 3D tree structures.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115905799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A multi-stage leakage aware resource management technique for reconfigurable architectures 面向可重构体系结构的多级泄漏感知资源管理技术

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591526

Pham Nam Khanh, Ashutosh Kumar Singh, Akash Kumar

{"title":"A multi-stage leakage aware resource management technique for reconfigurable architectures","authors":"Pham Nam Khanh, Ashutosh Kumar Singh, Akash Kumar","doi":"10.1145/2591513.2591526","DOIUrl":"https://doi.org/10.1145/2591513.2591526","url":null,"abstract":"Shrinking size of transistors has enabled us to integrate more and more logic elements into FPGA chips leading to higher computing power. However, it also brings serious concern to the leakage power dissipation of the FPGA devices. One of the major reasons for leakage power dissipation in FPGA is the utilization of prefetching technique to minimize the reconfiguration overhead (delay) in Partially Reconfigurable (PR) FPGAs. This technique creates delays between the reconfiguration and execution parts of a task, which may lead up to 44% leakage power of FPGA since the SRAM-cells containing reconfiguration information cannot be powered down. In this work, a resource management approach containing scheduling, placement and post-placement stages has been proposed to address the aforementioned issue. In scheduling stage, a leakage-aware cost function is derived to cope with the leakage power. The placement stage uses a cost function that allows designers to decide a trade-off between performance and leakage-saving. The post-placement stage employs a heuristic approach and shows further improvements. Experiments show that our approach can achieve large leakage savings for both synthetic and real life applications with acceptable extended deadline. Furthermore, different variants of the proposed approach can reduce leakage power by 40-65% when compared to a performance-driven approach and by 15-43% when compared to state-of-the-art works.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1047 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A task-oriented vision system 任务导向的视觉系统

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591602

Yang Xiao, K. Irick, J. Sampson, N. Vijaykrishnan, Chuanjun Zhang

引用次数: 0

Transient analysis of gate inside junctionless transistor (GI-JLT) 栅极内无结晶体管(GI-JLT)瞬态分析

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591557

Pankaj Kumar, P. Kondekar, Sangeeta Singh

引用次数: 1