A feasibility study on robust programmable delay element design based on neuron-MOS mechanism

Abstract

The feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. In order to reduce the temperature sensitivity, another Neuron-MOS-based PDE circuit is also suggested by employing a temperature insensitive reference-current-generator. This type of PDE circuit achieves a delay change within 0.1% when the temperature fluctuates from 25 to 75 degree. In general, both types of suggested PDE circuits achieve better or fair performances over the robustness, power consumption and delay range.