Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory

The OpenRISC processor core, featuring a flat pipeline and a low area footprint has been integrated in a multi-core ultra-low power (ULP) cluster with a shared multi-banked memory to exploit parallelism in the near-threshold regime. The micro-architecture has been optimized to support a shared L1 memory and to achieve a high value of instructions per cycle (IPC) per core. The proposed architecture achieves IPC results in the range of 0.88 and 1 in a set of benchmark applications which is an improvement of up to 83% with respect to the original OpenRISC implementation. Implemented in 28nm FDSOI technology, the proposed design achieves 177 MOPS when supplied at 0.6V near-threshold voltage. The energy efficiency at this workload is 90.07 MOPS/mW which is an improvement of 50% with respect to what can be achieved with an OpenRISC cluster based on the original micro-architecture.