2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献_第3页

All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors 用于跟踪处理器最小能量点的全数字片上异构传感器

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383780

Shu Hokimoto, Jun Shiomi, T. Ishihara, H. Onodera

{"title":"All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors","authors":"Shu Hokimoto, Jun Shiomi, T. Ishihara, H. Onodera","doi":"10.1109/ICMTS.2018.8383780","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383780","url":null,"abstract":"Dynamically scaling the supply voltage (VDD) and the threshold voltage (VTH) is one of the most effective approaches for reducing the energy consumption of processors. However, since the best pair of VDD and VTH, which minimizes the energy consumption of processors is strongly dependent on the operating condition such as an activity factor and a performance required for the processor, it is not trivial to find the best pair of the voltages at runtime when the operating condition widely varies. With all-digital on-chip heterogeneous sensors, we propose a simple runtime method to accurately identify the best pair of VDD and VTH, which minimizes the energy consumption of a processor under a specific operating condition which is determined by a process variation, an activity factor, and a performance requirement for the processor. Measured results for a 32-bit RISC processor integrating the heterogeneous sensors show that the proposed method successfully tracks the minimum energy operating point (i.e. the best pair of VDD and VTH) of the processor even in a case that the operating condition widely varies.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122089116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Test structures without metal contacts for DC measurement of 2D-materials deposited on silicon 无金属触点的测试结构，用于沉积在硅上的2d材料的直流测量

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383767

L. Nanver, X. Liu, T. Knežević

引用次数: 5

Open model for external mechanical stress of semiconductors and MEMS 半导体和MEMS外部机械应力的开放模型

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383795

R. Buhler, R. Giacomini

引用次数: 0

Algorithm based adaptive parametric testing for outlier detection and test time reduction 基于自适应参数测试算法的离群点检测与测试时间缩短

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383784

V. Katragadda, M. Muthee, A. Gasasira, Frank Seelmann, J. Liao

{"title":"Algorithm based adaptive parametric testing for outlier detection and test time reduction","authors":"V. Katragadda, M. Muthee, A. Gasasira, Frank Seelmann, J. Liao","doi":"10.1109/ICMTS.2018.8383784","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383784","url":null,"abstract":"Parallel test capability, enabled by numerous independent measurement channels has significantly increased throughput in parametric testing. It involves testing of numerous devices simultaneously synchronously or asynchronously. The number of devices tested for a given pad layout is increased by using higher dimensional arrays, the hallmark of which is pad sharing. Parallel testing of multiple devices with shared pads is vulnerable to device fails, where a failing device adversely affects measurement of all other devices. Information about this failing device or compromised measurement would only be evident at post analysis where a retest with a recipe change can then be ordered. In some cases retest is impossible as wafers would have already moved on to subsequent processing steps, thereby losing valuable learning opportunity. On the other hand, having to wait for post analysis requires time. Ideally failure detection and subsequent re-measure is done dynamically while the device is under test. This would require that decision making capability to be implemented in an automated tester equipment. In this work, we will discuss an algorithm based approach to adaptively change the test program allowing testing or skipping devices based on data collected real time while device is under test. The adaptive algorithm is also extended to aid in test time efficiency by eliminating tests based on measurement results of preceding tests.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129390424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Electrostatic test structures for transmission line pulse and human body model testing at wafer level 传输线脉冲和人体模型试验用静电试验装置

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383762

R. Ashton, Stephen Fairbanks, Adam Bergen, E. Grund

引用次数: 2

Versatile chip-level integrated test vehicle for dynamic thermal evaluation 用于动态热评估的多功能芯片级集成测试车

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383779

Suresh Parameswaran, S. Balakrishnan, Boon Ang

{"title":"Versatile chip-level integrated test vehicle for dynamic thermal evaluation","authors":"Suresh Parameswaran, S. Balakrishnan, Boon Ang","doi":"10.1109/ICMTS.2018.8383779","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383779","url":null,"abstract":"Thermal management of semiconductor chips is becoming very important as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle — starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the circuit architecture/implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability — enabling it to generate up to 3W per mm2 and has a temperature detection range of 30C to 125C with an accuracy of +/−2C. It has a simple implementation and is easy to program and test — yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip temperature measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to emulate many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating power-aware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics 结合环振荡器延迟和触发器保持特性的过程变化估计

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383773

Takuma Konno, S. Nishizawa, Kazuhito Ito

引用次数: 1

NPN mismatch dependence on layout NPN失配依赖于布局

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383774

Cory Compton

引用次数: 1

Passive permutation multiplexer to detect hard and soft open fails on short flow characterization vehicle test chips 在短流量表征车辆测试芯片上采用被动排列多路复用器检测硬、软开启故障

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383752

C. Hess, Shia Yu

引用次数: 1

An on-chip test structure for studying the frictional behavior of deep-RIE MEMS sidewall surfaces 用于研究深rie MEMS侧壁表面摩擦行为的片上测试结构

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383792

R. R. Reddy, Y. Okamoto, Y. Mita

引用次数: 3