发布求助
文献互助 智能选刊 最新文献

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献

筛选
英文 中文
Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs 用于调试由finfet中布局相关效应引起的关键器件变化的测试结构
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-19 DOI: 10.1109/ICMTS.2018.8383751
Qi Lin, Hans Pan, Jonathan Chang
{"title":"Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs","authors":"Qi Lin, Hans Pan, Jonathan Chang","doi":"10.1109/ICMTS.2018.8383751","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383751","url":null,"abstract":"The increasing stress engineering in FinFETs raises concerns about performance variation caused by the strong layout-dependent effect (LDE). The challenge is that it is difficult to decouple the combination of LDEs in a layout. As a result, it is challenging for Fab to reduce the variation induced by LDE. In this paper, we present a set of test structures for monitoring and debugging the variation of critical devices caused by LDEs. These test structures were verified in 16nm FinFET technology. We also present two case studies of debugging FinFET device variation by using these test structures.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sensitivity of high-k encapsulated MoS2 transistors to I-V measurement execution time 高k封装MoS2晶体管对I-V测量执行时间的敏感性
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-19 DOI: 10.1109/ICMTS.2018.8383789
P. Bolshakov, A. Khosravi, P. Zhao, R. Wallace, C. Young, P. Hurley
{"title":"Sensitivity of high-k encapsulated MoS2 transistors to I-V measurement execution time","authors":"P. Bolshakov, A. Khosravi, P. Zhao, R. Wallace, C. Young, P. Hurley","doi":"10.1109/ICMTS.2018.8383789","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383789","url":null,"abstract":"High-k encapsulated M0S2 field-effect-transistors were fabricated and electrically characterized. Comparison between HfO2 and AkO3 encapsulated MoS2 FETs and their I-V response to execution time are shown. Changes in gate voltage step and integration time demonstrate that electrical characterization parameters can significantly impact device parameters such as the subthreshold swing and the threshold voltage.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer level characterisation of microelectrodes for electrochemical sensing applications 用于电化学传感应用的微电极的晶圆级表征
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-19 DOI: 10.1109/ICMTS.2018.8383793
E. Blair, L. Basanta, I. Schmueser, J. Marland, A. Buchoux, A. Tsiamis, C. Dunare, M. Normand, A. Stokes, A. Walton, Stewart Smith
{"title":"Wafer level characterisation of microelectrodes for electrochemical sensing applications","authors":"E. Blair, L. Basanta, I. Schmueser, J. Marland, A. Buchoux, A. Tsiamis, C. Dunare, M. Normand, A. Stokes, A. Walton, Stewart Smith","doi":"10.1109/ICMTS.2018.8383793","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383793","url":null,"abstract":"This work presents a system for the in-line wafer-level characterisation of electrochemical sensors. Typically, such sensors are first diced and packaged before being electro-chemically tested. By integrating their characterisation into the manufacturing process, the production of electrochemical sensors becomes more efficient and less expensive as they can be parametrically tested midway through the fabrication process, without the need to package them. This enables malfunctioning or failed devices to be identified before dicing and reduces costs as only functional devices are packaged (in many cases this can be more expensive than the sensor fabrication). This study describes wafer-level characterisation of a simple electrochemical sensor design using a photoresist hydrophobic corralling film for the electrolyte and a probe station for contacting to individual dies.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130449433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures 通过对各种不规则LOD测试结构的表征，验证BSIM4不规则LOD SPICE模型
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383758
Bob Peddenpohl, Max Otrokov, Jeremy Wells
{"title":"Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures","authors":"Bob Peddenpohl, Max Otrokov, Jeremy Wells","doi":"10.1109/ICMTS.2018.8383758","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383758","url":null,"abstract":"Stress from FET Isolation regions affects the electrical behavior of transistors in modern technologies. Characterization and modeling of stress effects have primarily been done for transistor layouts that have rectangular (regular) shaped source and drains. However, circuits may include transistor layouts that have non-rectangular (irregular) shaped source and drains. This paper presents test structures to evaluate the effects caused by isolation stress on irregular source/drain transistor layouts, and shows that the standard way of calculating the effective distances for modeling stress effects is also reasonable for irregular source/drain transistor layouts.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout 总电离剂量对采用封闭栅极和标准布局的 65 纳米体 CMOS 模拟性能的影响
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383790
M. Bucher, Aristeidis Nikolaou, A. Papadopoulou, N. Makris, Loukas Chevas, G. Borghello, H. D. Koch, F. Faccio
{"title":"Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout","authors":"M. Bucher, Aristeidis Nikolaou, A. Papadopoulou, N. Makris, Loukas Chevas, G. Borghello, H. D. Koch, F. Faccio","doi":"10.1109/ICMTS.2018.8383790","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383790","url":null,"abstract":"High doses of ionizing irradiation cause significant shifts in design parameters of standard bulk silicon CMOS. Analog performance of a commercial 65 nm CMOS technology is examined for standard and enclosed gate layouts, with Total Ionizing Dose (TID) up to 500 Mrad(SiO2). The paper provides insight into geometrical and bias dependence of key design parameters such as threshold voltage, DIBL, transconductance efficiency, slope factor, and intrinsic gain. A modeling approach for an efficient representation of saturation transfer characteristics under TID from weak through moderate and strong inversion and over channel length is discussed.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates 评估柔性衬底上石墨烯场效应晶体管的Al2O3介电体的测试结构
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383768
Xinxin Yang, M. Bonmann, A. Vorobiev, K. Jeppson, J. Stake
{"title":"Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates","authors":"Xinxin Yang, M. Bonmann, A. Vorobiev, K. Jeppson, J. Stake","doi":"10.1109/ICMTS.2018.8383768","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383768","url":null,"abstract":"We have developed a test structure for evaluating the quality of Al2O3 gate dielectrics grown on graphene for graphene field effect transistors on flexible substrates. The test structure consists of a metal/dielectric/ graphene stack on a PET substrate and requires only one lithography step for the patterning of the topside metal electrodes. Results from measurements of leakage current, capacitance and loss tangent are presented.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-chip reconfigurable monitor circuit for process variation and temperature estimation 用于工艺变化和温度估计的片上可重构监控电路
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383777
T. Kishimoto, T. Ishihara, H. Onodera
{"title":"On-chip reconfigurable monitor circuit for process variation and temperature estimation","authors":"T. Kishimoto, T. Ishihara, H. Onodera","doi":"10.1109/ICMTS.2018.8383777","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383777","url":null,"abstract":"This paper proposes a monitor circuit that can estimate process variation and temperature by circuit reconfiguration. The circuit topology of the temperature monitoring is crafted such that the oscillation frequency is determined by the amount of leakage current which has an exponential dependency to temperature. The voltage dependence of this circuit is small in the configuration for temperature measurement, and the temperature dependence is small in the configuration for process variation estimation. A test chip fabricated in a 65 nm CMOS process demonstrates the temperature estimation capability with accuracy within −0.3 °C to 0.4 °C over a temperature range of 10 ° C to 100 °C, as well as the ability for estimating process variations.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test structure for electrical assessment of UV laser direct fine patterned material 紫外激光直接精细图纹材料电气评定的测试结构
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383794
Naoto Usami, A. Higo, Ayako Mizushima, Y. Okamoto, Y. Mita
{"title":"Test structure for electrical assessment of UV laser direct fine patterned material","authors":"Naoto Usami, A. Higo, Ayako Mizushima, Y. Okamoto, Y. Mita","doi":"10.1109/ICMTS.2018.8383794","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383794","url":null,"abstract":"We propose a test structure to electrically assess direct laser fine patterning, which is entering a microelectronic era (below 10μm). Indium-Tin-Oxide (ITO) was used as a material example. High speed ITO patterning with laser ablation can contribute short turn-around-time development of opto-electrical devices, such as organic light emitting diode. However, not only machine-induced line-edge fluctuation but also the process (e.g. heat) induced material degradation may affect electrical linewidth. The aim of our test structure is to assess such critical dimension change through measurement of electrical property (i.e. conductivity). It consists of Kelvin-connection straight lines and Greek crosses with various widths. Ultraviolet (UV) laser process as well as lithography and plasma etching were applied with the same test structure. The measurement revealed that the applied direct patterning condition induced small damage, showing applicability of direct patterning in microelectronics R&D.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127355275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DFT-enabled within-die AC uniformity and performance monitor structure for advanced process 支持dft的模内交流均匀性和先进工艺的性能监控结构
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383778
N. Chong, I-Ru Chen, Da Cheng, Amitava Majumdar, Ping-Chin Yeh, Jonathan Chang
{"title":"DFT-enabled within-die AC uniformity and performance monitor structure for advanced process","authors":"N. Chong, I-Ru Chen, Da Cheng, Amitava Majumdar, Ping-Chin Yeh, Jonathan Chang","doi":"10.1109/ICMTS.2018.8383778","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383778","url":null,"abstract":"An on-chip ring oscillator based process monitoring vehicle embedded within host automatic place and route digital blocks and accessed through design for testability (DFT) circuit is introduced and characterized. Within-wafer AC uniformity (ACU), performance and power consumption for the ring oscillator are analyzed in a 7 nanometer technology testchip. The design and analysis techniques described are suitable to monitor process variation, real-time power fluctuation and performance proxy of host digital blocks in products.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131545188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monte Carlo analysis by direct measurement using Vth-shiftable SRAM cell TEG 蒙特卡罗分析直接测量使用vth可移动SRAM单元TEG
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2018-03-01 DOI: 10.1109/ICMTS.2018.8383772
S. Yamaguchi, Daisuke Nishikata, H. Imi, Kazuyuki Nakamura
{"title":"Monte Carlo analysis by direct measurement using Vth-shiftable SRAM cell TEG","authors":"S. Yamaguchi, Daisuke Nishikata, H. Imi, Kazuyuki Nakamura","doi":"10.1109/ICMTS.2018.8383772","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383772","url":null,"abstract":"The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement using Vth-shiftable SRAM cell TEG (VTST) was developed. The dynamic Vth-shift circuit (DVSC) using electrolytic capacitors and mechanical relays for setting individual Vth-shift voltages for six MOSFETs in a memory cell enables to share a programmable external voltage source. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信