Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures

Abstract

Stress from FET Isolation regions affects the electrical behavior of transistors in modern technologies. Characterization and modeling of stress effects have primarily been done for transistor layouts that have rectangular (regular) shaped source and drains. However, circuits may include transistor layouts that have non-rectangular (irregular) shaped source and drains. This paper presents test structures to evaluate the effects caused by isolation stress on irregular source/drain transistor layouts, and shows that the standard way of calculating the effective distances for modeling stress effects is also reasonable for irregular source/drain transistor layouts.