2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)最新文献_第3页

A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias 一个皮焦耳级，1 GHz, 32 KByte/spl次/ 64b DSP SRAM，具有自反向偏置

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221218

A. Bhavnagarwala, S. Kosonocky, M. Immediato, D. Knebel, A. Haen

引用次数: 39

3-Transistor antifuse OTP ROM array using standard CMOS process 采用标准CMOS工艺的3晶体管抗熔丝OTP ROM阵列

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221214

Jinbong Kim, Kwyro Lee

引用次数: 11

A low-power microcontroller having a 0.5 /spl mu/A standby current on-chip regulator with dual-reference scheme 具有0.5 /spl mu/A备用片上电流调节器的双参考方案的低功耗微控制器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221156

M. Hiraki, K. Fukui, T. Ito

引用次数: 6

Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application 内置占空比校正使用编码相位混合方案的DDR/DDR2同步DRAM应用

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221229

Kyu-hyoun Kim, G. Cho, Jung-Bae Lee, Sooin Cho

引用次数: 15

10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process 10 GHz, 20 mW，快速锁定，自适应增益锁相环，片上频率校准，用于0.18 /spl mu/m数字CMOS工艺中的敏捷频率合成

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221197

A. Ravi, G. Banerjee, R. Bishop, B. Bloechel, L. Carley, K. Soumyanath

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引用次数: 10

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits 用于集成射频电路的SOI CMOS技术中的三维垂直平行板电容器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221153

Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Liang-Hung Lu, Yue Tan, Meeyoung Yoon, K. Jenkins, Mahender Kumar, A. Ray, L. Wagner

引用次数: 35

A low jitter, fast recoverable, fully analog DLL using tracking ADC for high speed and low stand-by power DDR I/O interface 一个低抖动，快速恢复，全模拟DLL使用跟踪ADC为高速和低待机功率DDR I/O接口

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221228

Se Jun Kim, Sang-Hoon Hong, J. Wee, Jin-Hong Ahn, J. Chung

引用次数: 7

The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications 伞式电池:用于SOC应用的逻辑过程兼容的2T电池

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221170

S. Akiyama, N. Oodaira, T. Ishikawa, D. Hisamoto, T. Watanabe

引用次数: 1

A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers 用于低中频GSM和EDGE接收机的四阶连续时间复数σ - δ ADC

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221166

F. Esfahani, P. Basedau, R. Ryter, R. Becker

引用次数: 23

A novel access scheme suppressing disturbance for a cross-point type ferroelectric memory 交叉点型铁电存储器中一种新的抑制干扰的存取方案

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI: 10.1109/VLSIC.2003.1221192

N. Sakai, Y. Ishizuka, S. Matsushita, Y. Takano, S. Ogasawara, K. Honma, T. Geshi, Y. Inoue, K. Fukase

引用次数: 2