内置占空比校正使用编码相位混合方案的DDR/DDR2同步DRAM应用

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221229

Kyu-hyoun Kim, G. Cho, Jung-Bae Lee, Sooin Cho

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引用次数: 15

摘要

本文采用一种新提出的编码相位混合方案，描述了具有内置占空比校正功能的延迟锁相环。该方案显著提高了DCC范围，提高了DLL的总体性能。采用0.11 /spl mu/m工艺，在1G-bit DDR(双数据速率)同步DRAM内设计和制作了DLL，测量数据表明，与我们之前的工作(2001)相比，它具有无限的DCC范围，更快的开启速度和更小的抖动。

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Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application

This paper describes DLL (delay locked loop) with built-in DCC (duty cycle correction) capability using a newly proposed coded phase blending scheme. The proposed scheme dramatically improves the DCC range and also enhances the total DLL performance. The DLL has been designed and fabricated within 1G-bit DDR (double data rate) synchronous DRAM using 0.11 /spl mu/m process and the measurement data show that it has unlimited DCC range, faster turn-on speed and smaller jitter compared with our previous work (2001).

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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