用于集成射频电路的SOI CMOS技术中的三维垂直平行板电容器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221153

Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Liang-Hung Lu, Yue Tan, Meeyoung Yoon, K. Jenkins, Mahender Kumar, A. Ray, L. Wagner

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引用次数: 35

摘要

本文介绍了采用0.12 /spl mu/m SOI CMOS工艺制备的高q、高密度三维垂直平行板(VPP)电容器。有效电容密度为1.76 fF//spl mu/m/sup 2/。对于20pf VPP电容器，在1ghz时的质量因数为22。并首次提出了VPP电容模型，用于VPP电容的设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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