S. Akiyama, N. Oodaira, T. Ishikawa, D. Hisamoto, T. Watanabe
{"title":"伞式电池:用于SOC应用的逻辑过程兼容的2T电池","authors":"S. Akiyama, N. Oodaira, T. Ishikawa, D. Hisamoto, T. Watanabe","doi":"10.1109/VLSIC.2003.1221170","DOIUrl":null,"url":null,"abstract":"We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F/sup 2/, approximately 60% smaller than a 6T cell. Careful bias design and a sub-IV sensing scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications\",\"authors\":\"S. Akiyama, N. Oodaira, T. Ishikawa, D. Hisamoto, T. Watanabe\",\"doi\":\"10.1109/VLSIC.2003.1221170\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F/sup 2/, approximately 60% smaller than a 6T cell. Careful bias design and a sub-IV sensing scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221170\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221170","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications
We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F/sup 2/, approximately 60% smaller than a 6T cell. Careful bias design and a sub-IV sensing scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V.