A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221166

F. Esfahani, P. Basedau, R. Ryter, R. Becker

引用次数: 23

Abstract

A low-power fourth order continuous-time complex /spl Sigma//spl Delta/ ADC has been designed and fabricated for low-IF (LIF) GSM and EDGE receivers in a 0.25 /spl mu/m CMOS technology. This ADC has a bandwidth of 270 kHz centered around-100 kHz. The dynamic range (DNR) is 82 dB at a sampling rate of 13 MHz even though the digital decimation filter and other blocks are active on the chip. The power consumption is 4.6 mW at 2 V supply. To our knowledge this ADC has the best performance, which has been reported so far with a complex /spl Sigma//spl Delta/ ADC for LIF mode GSM and EDGE receivers.

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用于低中频GSM和EDGE接收机的四阶连续时间复数σ - δ ADC

采用0.25 /spl mu/m CMOS技术，设计并制造了一种低功耗四阶连续时间复数/spl Sigma//spl Delta/ ADC，用于低中频(LIF) GSM和EDGE接收器。该ADC的带宽为270 kHz，中心为-100 kHz。动态范围(DNR)为82 dB，采样率为13 MHz，即使芯片上的数字抽取滤波器和其他模块是活动的。功耗为4.6 mW在2v电源。据我们所知，该ADC具有最佳性能，迄今为止已报道了用于liff模式GSM和EDGE接收器的复杂/spl Sigma//spl Delta/ ADC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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