The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications

Abstract

We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F/sup 2/, approximately 60% smaller than a 6T cell. Careful bias design and a sub-IV sensing scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V.